This adds a couple of missing fields to cpuctrl and comments out mcause.
mcause will be added back once RISC-V DV has been updated to support
WARL fields properly.
Interrupts are disabled in Debug Mode (Sdext 4.1.2), and simultaneously
registers, including MCAUSE, are not updated by exceptions (Sdext 4.1.3),
so reading MCAUSE[31] after an exception (eg. invalid instruction) in
debug_mode may still report the previous cause (which could be an interrupt).
Seperate concerns so the flow of stepping spike and checking against
the ibex RVFI data is clearer. One 'step' of either system produces
different amounts of progress, and this conditional-checking-and-stepping
is needed to tie up the flows.
Extends RVFI connections further to include 30 mhpmcounterX registers.
Sets them up before every cosim step to let Spike know their real values.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
We already have a clocking block inside dut_if. This commit uses it
to avoid a race condition that happens when `instr_valid_i` goes high
while `ecall_insn_i` goes low.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
We were not being able to hit the bin because in order to do that
we needed to have a posedge clk when the condition happened. Now,
we are latching the condition to register it after we wake up from
sleep.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
Adds some signal to the load store unit to catch when we have the
fetch error signals from both first and second part of the misaligned
load/store access cases.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
- Adds comments for quicker explanation of test and library functionality
- Refactor types and naming of control knob signals for clarity
- Move constraints from MEMBER to CLASS for more flexibility
- Add missing license header
Signed-off-by: Harry Callahan <hcallahan@lowrisc.org>
Includes coverpoints for:
- Hardware trigger point matches
- Debug simple step entrance in controller
- Seeing different insns while single stepping
Also updates on coverage plan to fill up missing mentions of
coverpoints/crosses
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
Update code from upstream repository https://github.com/google/riscv-
dv to revision 0b2b3d65ce8fdff4de8974d1f328a90d6c1db5dd
* [epmp] Add support for mseccfg CSR (Pirmin Vogel)
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
If you call the read() function on the memory model with an
uninitialised word, it generates a UVM error.
This is reasonable for data memory (where we never want to read
something without an architectural value) but is not reasonable for
IMEM, where Ibex runs ahead. Squash the error in this case, but force
bad integrity for the fetch to make sure we see something explode.
This works with versions ibex-cosim-v0.2 and ibex-cosim-v0.3. The latter
version is required to support the mseccfg CSR added with ePMP.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This makes use of functions in a way that enables us to use `priv_lvl`
dependent logic in the DV environment.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
I was previously just dumping them to /dev/null because the
code always worked but... predictably I was wrong! Write them
somewhere more useful for debug.
This allows us to model stuff more closely. This depends on Spike
version ibex-cosim-v0.2 (which is rebased onto a master branch commit
supporting these more specific ISA strings).
Don't yet tear out the old logfile-comparision code, add a new path for the
cosim flow.
This uses the existing riscv-dv functions to parse the cosim logfile, as it is
fundamentally still generated by spike so should be checked for errors.
This is a continuation of PR's #1613 and #1575 work.
If cosim in enabled, we need to pass the appropriate flags to the eda tool for
it to link against the precompiled ISS when building the testbench.
This commit assembles the appropriate flags using pkg-config to query the
SPIKE_ISS build, then uses the scripts_lib.subst_vars() method to populate the
templated commands in the yaml.
The eda tools have different requirements for consuming the flags, so massage
them into the appropriate shape on the python side.
Updated the parameters with respect to top_earlgrey.hjson in OpenTitan
repository. For other builds, kept the previously undeclared parameters
as their default values.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
