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Author SHA1 Message Date
Pirmin Vogel
0a1a8514c4 [rtl] Rework access to performance counter CSRs 
This commit reworks the code section describing how the performance
counter CSRs are accessed by CSR instructions. Instead of using an
address mask inside the default case, and excluding CSRs in the same
address range previously handled (like `mcycle(h)`, `minstret(h)`,
`mcountinhibit`), all performance counter CSRs are now explicitly
enumerated. This enhances readability of the code and enhances
compatibility with some tools without changing behavior or causing
lint problems.

This commit is based on suggestions from @MarekPikula. It replaces the
proposal in lowRISC/ibex#336.
 2019-11-11 19:01:49 +01:00
Greg Chadwick
2041f10c69 Added simple system 
Simple system is a basic verilator top-level testbench for running
 executables.  It has functionality for outputting text to a log file
 and for the software to terminate the simulation
 2019-11-09 07:48:47 +00:00
Greg Chadwick
31d423ae47 Added top-level shared directory 
shared is to be used for RTL/Code that is used by multiple parts of the
directory tree or does not fit neatly under other places in the tree.
 2019-11-09 07:48:47 +00:00
udinator
502b5a951e
[DV] clean up stale TODOs (#448) 2019-11-04 16:52:01 -08:00
udinator
498786aef5 Update google_riscv-dv to google/riscv-dv@44bec76 (#447) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 44bec7695fd2399166e181fa84b66a608b5f745f

* Re-enable custom OVPsim configuration files (google/riscv-dv#282)
  (udinator)
 2019-11-04 13:41:36 -08:00
udinator
098fb7d847
[DV/flow] Integrate with RISCV-DV (#446) 2019-11-04 13:22:47 -08:00
udinator
f3f3f3de09
Update google_riscv-dv to google/riscv-dv@cce71d2 (#445) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision cce71d24b56f641d994fbf69b8b50aa3756b9322

* Add handshake documentation (Udi)
* Fix coverage debug mode (google/riscv-dv#281) (taoliug)
* Fix coverage script issue (google/riscv-dv#280) (taoliug)
* code block highlight (google/riscv-dv#279) (taoliug)
* Replace setting directory with a default target (google/riscv-
  dv#278) (taoliug)
* fixed trace handling issues (google/riscv-dv#274) (eroom)
* Allow running the script from other directory (google/riscv-dv#277)
  (taoliug)
* Add dummy writes to status and ie CSRs (Udi)
* Script typo fix (google/riscv-dv#272) (Dan Petrisko)
* Fix misa setup issue (google/riscv-dv#271) (taoliug)
* Enable mie.mtie for timer interrupts (Udi)
* Update illegal system instr generation (Udi)
* Fix duplicate (google/riscv-dv#268) (taoliug)
* Add experimental instruction distribution control (google/riscv-
  dv#267) (taoliug)
* Update README to clarify the flow setup instructions (google/riscv-
  dv#265) (taoliug)
* Remove debug logging (google/riscv-dv#264) (taoliug)
* Fix compressed instruction test setup (google/riscv-dv#263)
  (taoliug)
* adding __init__ in the scripts dir since python3.7 requires that for
  directories to be recognized as modules (google/riscv-dv#252)
  (Jielun Tan)
* Fix riscvOVPsim.ic (google/riscv-dv#261) (taoliug)
* Fix ovpsim sim problem (google/riscv-dv#260) (taoliug)
* Add alternative command options for directed instruction stream
  (google/riscv-dv#254) (taoliug)
* Fix dsim compilation issue (google/riscv-dv#253) (taoliug)
 2019-11-04 10:48:02 -08:00
Tom Roberts
48adda0b47 [verilator] Fix a few verilator DV issues 
- Speed up compile time by only optimizing hot code
- Fix some incorrect references in tb_cs_registers
- Add a comment for FST vs VCD tracing
 2019-11-01 16:02:46 +00:00
Pirmin Vogel
275c3310fa [rtl] Remove unused set-less-or-equal-than ALU ops 
These operations (ALU_SLET, ALU_SLETU) are remnants of of the original
OpenRISC design. RISC-V just has set-less-than (ALU_SLT, ALU_SLTU).

This resolves lowRISC/ibex#432 reported by @udinator.
 2019-11-01 11:51:25 +00:00
udinator
e2ab24b9e3
[DV] Assert interrupt during write to MSTATUS and MIE (#435) 2019-10-31 11:14:53 -07:00
Greg Chadwick
5ce6351530 Add performance counter utils for verilator sims 2019-10-30 16:56:55 +00:00
Tom Roberts
70b53068db [DV] Add registers testbench 
- Sample C++ unit testbench for system registers module
- Only tests a few PMP registers at the moment
 2019-10-30 14:46:33 +00:00
Pascal Cotret
e5cf0c0fcf Error synthesis in Vivado 2019-10-28 20:36:37 +00:00
Pirmin Vogel
36ce999fbb [rtl/lsu] Rework assertion checking response valid 
This commit replaces an obsolete assertion with one checking that
response valid is received only if the LSU is ready to handle it.

This resolves lowRISC/ibex#421 reported by @udinator.
 2019-10-26 14:51:19 +01:00
udinator
edf9371c6c
[DV] Increase number of resets in reset_test (#418) 2019-10-25 14:28:06 -07:00
udinator
d3c7b887d7
[DV] Increase number of illegal instructions generated (#426) 2019-10-25 14:00:22 -07:00
Pirmin Vogel
0331ed61b1 [rtl/alu] Remove unused comparison operations 
These operations (ALU_GT, ALU_GTU, ALU_LE, ALU_LEU) are remnants of
of the original OpenRISC design. RISC-V does not have these instructions
and instead implements the operations by reversing operands for ALU_LT,
ALU_LTU, ALU_GE, ALU_GEU.

This resolves lowRISC/ibex#420 reported by @udinator.
 2019-10-25 13:58:59 +01:00
Marek Pikuła
294849bb18 [RTL] Add MultiplierImplementation parameter in top level 2019-10-24 14:33:24 +01:00
udinator
c89e431937
Update google_riscv-dv to google/riscv-dv@46ec4bc (#417) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 46ec4bc48bc1eebc5a2bcd48fe4ce4c77105fead

* Incorrect deletion (google/riscv-dv#249) (eroom)
* Updated OVPsim log processing for coverage (google/riscv-dv#248)
  (eroom)
* Improve illegal/hint test coverage (google/riscv-dv#247) (taoliug)
* Coverage model fixes (google/riscv-dv#246) (taoliug)
* Add back-to-back jump instruction test (google/riscv-dv#244)
  (taoliug)
* Functional coverage improvement (google/riscv-dv#243) (taoliug)
* Functional coverage improvement (google/riscv-dv#242) (taoliug)
* Support c.jr,c.jalr, fix coverage sampling issues (google/riscv-
  dv#241) (taoliug)
* allow select a random GPR for JALR op (google/riscv-dv#240)
  (taoliug)
* Fix coverage definition/sampling issue (google/riscv-dv#239)
  (taoliug)
* Testlist clean up, add RV32I target (google/riscv-dv#238) (taoliug)
* Consolidate the coverage collection script (google/riscv-dv#234)
  (taoliug)
* Fixed default values, and trailing blank lines (google/riscv-dv#233)
  (eroom)
* Refine README structure (google/riscv-dv#231) (taoliug)
* Add pre-defined target: RV32IMC, RV64IMC (google/riscv-dv#230)
  (taoliug)
 2019-10-23 10:46:31 -07:00
udinator
023b7b6856
[RTL/Tracer] Fix compressed jump RD write (#416) 2019-10-23 10:30:11 -07:00
udinator
8e40f65582
[DV] Enable timer interrupts (#415) 2019-10-23 09:33:50 -07:00
Tobias Wölfel
0728fb7e9f [DV] Update simulation terminate argument 
Add description to usage output.
Add short option '-c'.
 2019-10-21 22:19:24 +02:00
udinator
c808fed7d1
[DV] testplan documentation (#409) 2019-10-21 11:45:40 -07:00
udinator
beb40d89f6
[DV] Add interrupt wfi test to address coverage hole (#410) 2019-10-21 11:44:23 -07:00
Philipp Wagner
1c3903e2ce Tracer: Decode an all-zero instruction as c.unimp 
Fixes #396
 2019-10-17 13:48:29 +01:00
Greg Chadwick
edb33cca56 Add Greg Chadwick to CREDITS.md 2019-10-17 11:07:05 +01:00
Greg Chadwick
6b1a7add5d [Doc] Added extra setup info for Verification 2019-10-17 10:31:18 +01:00
udinator
b2e36ec345
Update google_riscv-dv to google/riscv-dv@033fccf (#406) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 033fccfbd50f6412e66b448a1d04245d787004bd

* Add more ebreak generation control (google/riscv-dv#229) (udinator)
* Fix timemout, misc update to README (google/riscv-dv#228) (taoliug)
* Fix CSR test setup (Udi)
* Update spike setup instruction for commit log (google/riscv-dv#226)
  (taoliug)
* Fix spike arguments to generate commit log (google/riscv-dv#225)
  (Greg Chadwick)
* Minor README typo (google/riscv-dv#219) (Dan Petrisko)
* Add random FCSR programing, add RV32FC/DC support (google/riscv-
  dv#221) (taoliug)
* Add floating point load/store support (google/riscv-dv#220)
  (taoliug)
* Fix floating point comparison issue (google/riscv-dv#218) (taoliug)
* Add basic support for F/D extension (google/riscv-dv#217) (taoliug)
* Generate the ucdb file inside output directory (google/riscv-dv#215)
  (Hai Hoang Dang)
* cov.py: Allow coverage to run with different simulator
  (google/riscv-dv#214) (Hai Hoang Dang)
 2019-10-16 17:50:23 -07:00
udinator
fc80203af3
[DV] Debug_ebreak test fix (#405) 2019-10-16 17:44:47 -07:00
taoliug
1b71320230
Add RV32IM test (#404) 2019-10-16 10:15:49 -07:00
Philipp Wagner
59fdbb517f Licensing documentation: Add commercial support info 
lowRISC provides commercial support for Ibex, mention that in the
licensing page if people are looking for such an offering.

Can be extended in the future as we know of more companies offering
support.
 2019-10-16 15:08:45 +01:00
Philipp Wagner
2cc282aeee Improve copyright/licensing page 
Rename the page to "Licensing", and improve its contents to be more
helpful to people not familiar with open source projects and the Apache
license.
 2019-10-16 15:08:45 +01:00
Greg Chadwick
cc94bc8d54 [RTL] Fix single stepping on exceptions 
When we single step over an instruction that causes an exception DPC
should be set to point to the exception handler (where we would have
gone were we not single stepping).
 2019-10-16 10:23:05 +01:00
Greg Chadwick
b94961402c [RTL] Fix ebreak behaviour in U-mode 
Fixes #370

Whether EBREAK enters debug mode is controlled by the
ebreaku and ebreakm dcsr fields. Which is relevant depends upon the
privilege level.
 2019-10-16 09:10:34 +01:00
Greg Chadwick
7aa87156d3 [RTL] Fix ebreak and cleanup debug 
Fixes #393

When entering debug mode in controller need to ensure ID doesn't get
flushed until the relevant debug state can see the contents of ID and
perform the appropriate actions. ID is flushed at that point.

Also cleaned up some code replication around entering debug mode
(debug_req vs single step look very similar so can use the same code
paths).
 2019-10-16 09:10:34 +01:00
udinator
6b8b3762ec
[DV] Fix bugs in mem_error test to circumvent test deadlock (#400) 2019-10-15 15:19:36 -07:00
Greg Chadwick
2bc785e7d9 [RTL] Prevent CSR write on any illegal CSR reason 
Debug register access sets illegal_csr if not in debug mode but CSR
write still went ahead. This modifies the CSR write to ensure that
anything that results in an illegal CSR instruction being signalled will
prevent a CSR write.
 2019-10-15 14:43:55 +01:00
udinator
bbb688a2aa
[DV] Fix lint warnings (#397) 2019-10-14 10:20:28 -07:00
Pirmin Vogel
5f0be50473 Remove non-ASCII characters from .sv and .rst files 2019-10-14 09:08:16 +01:00
udinator
5972c63ba8
[DV] Let time-consuming checker tasks detect failures (#395) 2019-10-11 13:48:20 -07:00
udinator
ae82d61401
[DV] Add reset test (#392) 2019-10-10 13:01:32 -07:00
udinator
2ca1a6da21
[DV] Update csr description for U-mode changes (#387) 2019-10-10 09:18:48 -07:00
udinator
566e73c352
[RTL] Enable reading mstatus.tw (#388) 2019-10-10 09:17:14 -07:00
Alex Bradbury
0abe5ccaf7 [CI] Stop pinning an old attrs version 
simplesat (required by fusesoc) was broken by an update to the attrs
library. Now simplesat 0.8.2 has been released which fixes the issue, we
can remove the explicit pinning of the old attrs version.
 2019-10-10 16:22:56 +01:00
Philipp Wagner
2b6a95190e Remove outdated waiver 
With the introduction of U mode this signal is always read.
 2019-10-09 13:35:01 +01:00
Philipp Wagner
3db46f91e0 Tie off csr_pmp_* signals for all lint tools 
Our generic way of marking signals as unused is assigning them to an
unused_* signal. That works for all lint tools and avoids tool-specific
waivers.
 2019-10-09 13:35:01 +01:00
Philipp Wagner
90ff45abbd Avoid self-determined bit length of signals 
This works around a lint error we get; the old and the new version are
equally wrong or right, but it doesn't seem to be worth fighting with a tool.
 2019-10-09 13:35:01 +01:00
Philipp Wagner
cdc8078c0f ibex_cs_registers: Add missing generate name 
One condition is missing a generate label.
 2019-10-09 13:35:01 +01:00
Tom Roberts
c33525ae80 [RTL LSU] Change unaligned error behaviour 
- If an error is signalled in the first part of an unaligned
  transaction, the second part is issued anyway (to avoid a
  timing loop from data_err_i -> data_req_o)
- Previously, the error was signalled and an exception was taken
  as soon as the first transaction completed. This commits makes
  the core wait until both transactions have completed.
- This prevents strange behaviour caused by the lsu and controller
  being out of sync (fixes #374).
 2019-10-09 10:07:07 +01:00
udinator
4a1806f16f
Update google_riscv-dv to google/riscv-dv@ad6fe56 (#385) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision ad6fe565a91445cc3ea3e32119360b57af4f19b2

* Workaround for dsim compile issue (google/riscv-dv#211) (taoliug)
* Add a --seed_yaml option to rerun a regression with the same seed of
  a prior regression (google/riscv-dv#210) (taoliug)
* Update questa covearge options (google/riscv-dv#209) (taoliug)
* Fix disable_compressed_instr option (google/riscv-dv#205) (taoliug)
* Fix non-compressed instruction test (google/riscv-dv#203) (taoliug)
* Debug single step functionality and config knobs (Udi)
* Fix no_branch_jump option (google/riscv-dv#200) (taoliug)
* Add more functional covergroup (google/riscv-dv#199) (taoliug)
* Allow randomly reserve GPR for TP/SP, improve functional coverage
  (google/riscv-dv#198) (taoliug)
* Allow running the coverage script with LSF (google/riscv-dv#195)
  (taoliug)
* Add support for disable_compressed_instr (google/riscv-dv#194)
  (taoliug)
* Improve coverage collection performance (google/riscv-dv#193)
  (taoliug)
* Signature_addr_reg constraint update (Udi)
* Add a debug mode for functional coverage (google/riscv-dv#191)
  (taoliug)
* Fix typo in README (google/riscv-dv#189) (taoliug)
* Constrain scratch_reg (google/riscv-dv#188) (udinator)
* Update README for the coverage flow (google/riscv-dv#187) (taoliug)
* Add basic privileged CSR cover group (google/riscv-dv#186) (taoliug)
* Fix cover point definition (google/riscv-dv#185) (taoliug)
* Fix ovpsim log compare issue (google/riscv-dv#183) (udinator)
 2019-10-08 14:22:05 -07:00