840 commits

Author	SHA1	Message	Date
stnolting	9ed7b84d1a	added runtime note to show CoreMark has not been actually compiled	2020-08-20 12:07:18 +02:00
stnolting	1c4adc5108	updated makefiles; now also supports assembly and *.cpp source files	2020-08-19 21:14:53 +02:00
stnolting	af2de3ca48	minor edits	2020-08-13 20:14:40 +02:00
stnolting	968eb68c2c	minor edits	2020-08-07 20:46:42 +02:00
stnolting	d931430dd5	removed cycle/instret CSR tests; added output to show number of executed instructions and cycles to final report	2020-08-06 20:32:47 +02:00
stnolting	4f604e3a23	simplified makefiles (using implicit definition of libc)	2020-08-06 19:06:39 +02:00
stnolting	4708465e8a	minor edits	2020-08-04 22:38:04 +02:00
stnolting	f2537df43e	using explicit IRQ enable	2020-07-30 21:25:04 +02:00
stnolting	8f0cd29b2c	minor edits and updates	2020-07-30 18:44:33 +02:00
stnolting	10545eb447	minor edits	2020-07-29 19:05:42 +02:00
stnolting	ed85da5589	added PMP test; minor edits and fixes	2020-07-29 19:03:51 +02:00
stnolting	17ad773155	minor edits	2020-07-25 11:03:14 +02:00
stnolting	8eb2b07e9e	updated for new RTE	2020-07-23 21:44:13 +02:00
stnolting	b0d0287773	minor edits and optimizations	2020-07-21 20:46:28 +02:00
stnolting	ceb5009b60	minor edits	2020-07-21 19:41:00 +02:00
stnolting	a8e6ad0546	added test for illegal compressed instruction exception	2020-07-20 22:32:54 +02:00
stnolting	d098e1d6b1	updates	2020-07-17 23:40:10 +02:00
stnolting	33d74f4604	minor updates due to new SYSINFO component	2020-07-17 23:39:54 +02:00
stnolting	ee790a973d	coremark now only uses performance data from the timed core to compute the average CPI	2020-07-17 17:17:56 +02:00
stnolting	3be3ff2f22	removed software interrupt test	2020-07-13 20:02:44 +02:00
stnolting	273efb9159	typo fix	2020-07-11 14:01:46 +02:00
stnolting	16fd74de3f	using only instret[h] and cycle[h] for performance evaluation	2020-07-11 13:06:52 +02:00
stnolting	48ae50154a	added further tests	2020-07-10 19:50:33 +02:00
stnolting	227516009b	misa CSR is read-only! mtval and mcause CSRs can now also be written by user; fixed error in bus unit - controller can now force bus unit reset and bus transaction termination	2020-07-09 14:21:13 +02:00
stnolting	2ff653f600	cpu test now also prints project credits	2020-07-08 16:16:51 +02:00
stnolting	d4e18558ac	added simple fence/fence.i test	2020-07-06 21:46:10 +02:00
stnolting	783dd11467	minor edits	2020-07-06 19:32:51 +02:00
stnolting	a3cb008f8a	bug fixes	2020-07-05 23:14:46 +02:00
stnolting	fa01809f60	updates due to new rte functions	2020-07-05 22:24:26 +02:00
stnolting	75d71a036c	updated makefiles	2020-07-05 22:22:21 +02:00
stnolting	d7cff7622a	removed hw_analysis and exception_test projects; they are replaced by the cpu_test project	2020-07-02 20:55:00 +02:00
stnolting	dbf1d47b01	added simple xilinx vivado simulator waveform configuration file	2020-07-02 20:54:17 +02:00
stnolting	a220448f82	minor edits	2020-07-01 21:44:51 +02:00
stnolting	def3cb5ee8	minor edits and updates	2020-06-25 20:16:17 +02:00
stnolting	ead0be3645	minor edits	2020-06-24 17:12:45 +02:00
stnolting	0da6665126	added example program for showing hardware configuration	2020-06-24 11:30:07 +02:00
stnolting	ea2948cdf9	modified travis CI test scripts	2020-06-23 22:43:59 +02:00
stnolting	417479a18b	added exceptions/interrupts test program	2020-06-23 19:38:35 +02:00
stnolting	5a80bb9a99	minor edits	2020-06-23 17:55:38 +02:00
stnolting	bee421876a	initial commit	2020-06-23 17:43:03 +02:00