Olof Kindgren
f6116cf2ec
Make right-shifts one cycle faster
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This allows removing the stage_two_req register as well.
2025-03-18 13:42:47 +01:00
Olof Kindgren
629e6727f5
Move shamt to top byte in bufreg2
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Instead of shifting shamt all the way to bits 4:0, we just shift
8 steps. This saves some energy and allows us to be finished before
cnt_done.
2025-03-18 13:40:44 +01:00
Olof Kindgren
a38110aea9
bufreg2: Split up dat_en to cnt_en and shift_en
2025-03-01 23:14:55 +01:00
Olof Kindgren
0a55885d3b
Move bytecnt to bufreg2
2025-03-01 23:12:44 +01:00
Olof Kindgren
2f23449f0f
Make branches, slt and left shifts one cycle faster
2025-03-01 23:12:44 +01:00
Olof Kindgren
91628a056a
Simplify one-hot counter enable
2025-03-01 23:12:44 +01:00
Olof Kindgren
129a9294c6
Remove slt_or_branch control signal
2025-03-01 23:12:44 +01:00
Olof Kindgren
1e4ea0527e
Fix CSR write detection in debug module
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2024-11-19 13:20:34 +01:00
Olof Kindgren
cd60abe837
Fix CSR width issues in debug module
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2024-10-17 14:34:08 +02:00
Olof Kindgren
9bf8672fb2
Move RVFI signals into serv_debug
2024-10-17 13:59:23 +02:00
Olof Kindgren
2bcf4104d0
Add debug module
2024-10-13 22:24:00 +02:00
Olof Kindgren
376dcd701d
Introduce width parameter
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Expose the width (or W internally) parameter to set the SERV
datapath width.
Note: Only width=1 is function at this time.
2024-10-05 23:17:22 +02:00
Olof Kindgren
1c5d44e5c4
Make CSR module 4-bit compatible
2024-10-05 11:27:51 +02:00
Olof Kindgren
40d34d204a
Avoid matching misa CSR as mstatus
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Reads from the (unimplemented) misa register matched mstatus which
in turn caused garbage data to be written to other CSRs. Make the
matching mask slightly stricter to avoid this particular issue.
2024-08-22 22:18:45 +02:00
Olof Kindgren
1fc6e7da9b
Set correct value of mstatus[mpp]
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The correct value of mstatus[mpp] for machine-mode is 11, but SERV
had this set to 00. Changes in the regression test suite uncovered
this error.
2024-08-22 22:18:45 +02:00
Nazar Kazakov
a26c2965c0
Fix typos
2024-04-06 16:35:45 +02:00
Olof Kindgren
bebc875353
Make serv_state more simulator-friendly
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Refactor the counter generation code to avoid using combinatorial
always statements that rely on an event happening at time 0. This
make serv work with Icarus again.
2024-03-19 12:40:50 +01:00
Olof Kindgren
4537abb965
bufreg refactoring in preparation of qerv integration
2024-03-06 20:22:23 +01:00
Olof Kindgren
b937ef61aa
Add width-agnostic serv_rf_ram_if
2024-02-23 14:35:38 +01:00
Olof Kindgren
907db143ea
Support w=4 in serv_rf_if
2024-02-22 13:27:04 +01:00
Olof Kindgren
f68a0889aa
Support w=4 in serv_ctrl
2024-02-22 13:12:07 +01:00
Olof Kindgren
6659811160
Add width-agnostic serv_csr
2024-02-22 12:29:20 +01:00
Olof Kindgren
adb3f4d5a4
Delete trailing whitespace from RTL
2023-12-03 18:21:01 +01:00
Olof Kindgren
bc74a9a1d7
Used named generate statements
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Unnamed generate statements are not recommended and some tools throw
warnings or errors for these.
2023-11-16 21:38:10 +01:00
Katherine Watson
7a6d5d3fc9
Make serv_alu.v synthesizable with Vivado
2023-11-16 14:41:46 +01:00
Olof Kindgren
c7fc57213c
Avoid releasing trap signal too early
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The trap signal is used my the mux in serv_rf_if to decide which
registers to write to. If the trap signal is dropped too early,
the destination address changes while the register is still being
written to.
2023-10-31 22:21:12 +01:00
uhit332
46a820ee42
support for W=4
2023-10-31 15:53:36 +01:00
uhit332
f9d6b23543
support for W=4
2023-10-31 13:23:17 +01:00
uhit332
2e23b5313a
alu with support for W=4
2023-10-31 12:42:52 +01:00
Olof Kindgren
4567214721
Refactor counter in serv_state
2023-07-13 10:29:19 +02:00
Olof Kindgren
8edd456b5d
Rewrite serv_rf_ram_if
...
This adds some optimizations to serv_rf_ram_if. It also adds a read enable
signal and delays writes one cycle which has the added bonus that no reads
or writes happen in the same cycle for RF_WIDTH > 2. This allows SERV to be
used with single-port RAMs in most cases.
2023-06-22 15:48:25 +02:00
Olof Kindgren
9be55f5cad
Set align parameter to the value of compressed by default
2022-12-25 21:34:48 +01:00
Olof Kindgren
76a75995b9
Remove RVFI interface from synth wrapper
2022-12-25 20:05:52 +01:00
Olof Kindgren
73508bc5de
Expose with_csr in servant
2022-07-26 00:28:53 +02:00
Abd
1beb9d33ec
privilege tests fixed for rv32i
2022-07-26 00:28:53 +02:00
Abd
82b410f500
Update reamde, comments and paramters
2022-06-13 10:38:11 +00:00
Abd
2655861447
Compressed Extension for SERV
2022-06-01 13:38:24 +02:00
Olof Kindgren
2bb988b553
Add reset for mie_mtie
2022-02-09 18:15:08 +01:00
Olof Kindgren
d910becd7f
Move dbus_dat/rs2/shamt storage to bufreg2
2022-01-02 22:10:33 +01:00
Olof Kindgren
f04a510393
Remove unused parameter from serv_mem_if
2022-01-01 22:50:28 +01:00
Olof Kindgren
7765567cf1
Add missing gate on mem_rd with CSR disabled
2021-12-29 00:17:00 +01:00
Olof Kindgren
28953fec4c
Simplify shift_op signal
2021-10-08 22:42:02 +02:00
Olof Kindgren
9c4bdd4bfe
Simplify branch_op/slt_op signals
2021-10-08 22:25:24 +02:00
Olof Kindgren
9d3ebf3e96
Replace mem_op with dedicated control signals
2021-10-05 12:52:29 +02:00
Olof Kindgren
e5c6e78820
Simplify MDU logic in serv_mem_if
2021-10-04 23:49:23 +02:00
Olof Kindgren
99f82af6eb
Simplify optional MDU logic
2021-10-03 23:28:45 +02:00
Zeeshan Rafique
8843005407
updated vars declaration for modelsim ( #63 )
2021-10-03 23:15:54 +02:00
Olof Kindgren
48e250ea5e
Clean up serv_state interface
2021-10-03 22:48:51 +02:00
Klas Nordmark
52d0bf0938
Added openlane target and params.tcl with suitable openlane parameters for SERV
2021-08-30 22:13:42 +02:00
Olof Kindgren
2989051f44
Avoid enabling bufreg before instruction is decoded
2021-08-27 13:10:06 +02:00
