291 commits

This branch

This branch

All branches

Author	SHA1	Message	Date
Olof Kindgren	88ffe617f5	WIP: Quickfeather support ... FIXME: Verify clock/reset	2021-04-23 09:20:40 +02:00
Olof Kindgren	51adf10772	Clear t0 in blinky example	2021-04-22 16:07:22 +02:00
Olof Kindgren	1c11365ae8	Simulator-friendly cleanup of misalign_trap_sync	2021-04-22 15:44:18 +02:00
Stefan Wallentowitz	cfb779d3d6	CI Lint with librecores github action linter ... Add the librecores linter, that also does proper annotation to the source code.	2021-04-18 23:02:04 +02:00
Olof Kindgren	0519ae4a52	Add verilator waiver file	2021-04-18 23:01:26 +02:00
Olof Kindgren	82c808aa1e	Implement byte_valid in a more efficient way	2021-04-18 22:48:55 +02:00
Olof Kindgren	62d5d5f8fb	Remove unused wire cnt4	2021-04-18 22:01:32 +02:00
Stefan Wallentowitz	5c303f46b4	Build website automatically and publish to gh-pages	2021-04-18 21:07:27 +02:00
Olof Kindgren	0c601f0872	Fix RF we gating for RF width > 2	2021-04-18 00:13:47 +02:00
Olof Kindgren	4c3ea39b06	Start documenting instruction life cycle	2021-04-18 00:10:10 +02:00
Olof Kindgren	079a5c4250	Remove unused wgo register	2021-04-08 15:36:11 +02:00
Olof Kindgren	9b84539bc0	Add LibreCores badge	2021-03-17 21:14:41 +01:00
Olof Kindgren	548b7fbb41	remove redundant ALU control signal	2021-03-14 23:22:50 +01:00
Olof Kindgren	727bb40a87	Simplify control logic for bool ops	2021-03-14 00:12:29 +01:00
Olof Kindgren	7624466ddd	Optimize serv_rf_ram_if	2021-02-15 08:50:24 +01:00
somhi	a6292d46a2	Add support for DECA Max 10 board	2021-02-07 18:20:33 +01:00
somhi	ceddc1876b	Sockit notes added	2021-02-07 18:20:33 +01:00
Olof Kindgren	9a0b0e877c	Move shifter to mem_if ... This allows reusing the data bus registers for shift amount	2021-02-06 23:24:23 +01:00
somhi	bc9705bef2	add support for SoCKit development kit board	2021-02-03 22:34:36 +01:00
Olof Kindgren	f70b79fd8f	Combine lt and eq regs to cmp_r in serv_alu	2021-02-01 22:37:45 +01:00
Olof Kindgren	308612fd9e	Expose WITH_CSR and RESET_STRATEGY in core file	2021-01-26 20:59:49 +01:00
Olof Kindgren	6fbdea58d6	Optimize trap handling	2021-01-23 22:42:26 +01:00
Olof Kindgren	8d5dd77a26	Optimize csr address handling	2021-01-23 22:42:26 +01:00
Olof Kindgren	e8bc87fd0e	Add serv_rf_if documentation	2021-01-20 23:48:28 +01:00
Olof Kindgren	e4b773c17b	Syntax fixes	2021-01-18 22:47:28 +01:00
Olof Kindgren	5e4181d204	Optimize shift operations	2021-01-18 22:46:51 +01:00
Olof Kindgren	d5febe8f63	Simplify and document trap handling	2021-01-18 22:38:07 +01:00
Olof Kindgren	4a5c5bd588	Update bufreg documentation	2021-01-11 22:09:24 +01:00
Olof Kindgren	17103dd1f5	Merge LSB registers into bufreg	2021-01-11 21:40:45 +01:00
Olof Kindgren	fe6c9b0f83	Optimize bufreg lsb signal and clean up bufreg interface	2021-01-06 22:19:40 +01:00
Olof Kindgren	0bc19ef13c	Clean up serv_alu interface	2021-01-06 22:02:13 +01:00
Olof Kindgren	ace7b8ef44	Explain and optimize state counter	2021-01-03 00:01:09 +01:00
Olof Kindgren	25fa6fa83b	Clean up and document serv_mem_if	2021-01-02 00:02:23 +01:00
Olof Kindgren	71de610129	Fix serv_dataflow	2020-12-31 00:48:44 +01:00
Olof Kindgren	89bf09922a	Clarify immdec and fix doc formatting	2020-12-30 14:31:07 +01:00
Olof Kindgren	ca1a07f684	Document and clean up interface of serv_immdec	2020-12-29 23:35:17 +01:00
Olof Kindgren	14cbe03a61	Sync up quartus-specific RAM to regular RAM module	2020-12-22 23:31:52 +01:00
Olof Kindgren	a960fd768b	Remove redundant bufreg_loop control signal	2020-12-22 22:13:57 +01:00
Olof Kindgren	c9f41b54e8	Optimize init signal	2020-12-22 22:13:57 +01:00
Jansen Arruda	9a920438fa	Update README.md ... Correct a typo in `fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc_cores` to `fusesoc library add fusesoc_cores https://github.com/fusesoc/fusesoc-cores`	2020-12-17 20:32:53 +01:00
Olof Kindgren	acab804a31	Port Zephyr support to 2.4 and update instructions	2020-12-16 23:02:56 +01:00
Bruno Flores	731ca8bb45	Allow for a configurable toolchain prefix.	2020-12-06 23:05:39 +01:00
Bruno Flores	fe90ff7f97	Add cmod-a7-35t target.	2020-12-06 23:05:38 +01:00
Kevin Läufer	d7e9b39c13	automate RISC-V compliance check with github actions	2020-12-06 22:54:04 +01:00
Olof Kindgren	d6445b95a6	Clean up serv_ctrl	2020-12-06 22:39:04 +01:00
Olof Kindgren	116e370589	Reverse polarity of bufreg_hold signal	2020-12-06 22:39:04 +01:00
mtnrbq	75ee4954d0	break out verilator fileset for use with v < 4.030	2020-12-06 22:29:28 +01:00
Olof Kindgren	aa16bc40b6	Move ibus_cyc handling to serv_state	2020-12-02 16:19:34 +01:00
Olof Kindgren	fd79a2ea0c	Use cnt0 in serv_ctrl	2020-12-01 22:40:52 +01:00
Olof Kindgren	bbe3e56ab2	Decouple ibus_cyc and ibus_ack	2020-11-30 23:13:11 +01:00