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Author SHA1 Message Date
Olof Kindgren
68d8af71f2 Use serv_rf_top in default and lint targets 2019-12-05 22:35:14 +01:00
Olof Kindgren
e93fd0d30e Fix compile errors with RISCV_FORMAL 2019-12-04 23:42:40 +01:00
Olof Kindgren
3179cfb107 Optimize alu eq_r and lt_r 2019-12-03 10:28:27 +01:00
Olof Kindgren
8b82c85fb6 Create toplevel without RF 2019-11-20 18:26:04 +01:00
Olof Kindgren
4532c8dafd Move rd selection to rf_if 2019-11-20 18:26:04 +01:00
Olof Kindgren
04037c4354 Split out RF to separate module 2019-11-20 18:26:04 +01:00
Olof Kindgren
fc348f3a22 Fix wen delays in rf 2019-11-20 18:26:04 +01:00
Olof Kindgren
a7d7d6475b Update Zephyr port to v1.14 2019-11-19 13:44:17 +01:00
Olof Kindgren
40000cbeb9 Fix IRQ 
This contains a lot of fixes as IRQ support was broken on both
RTL and zephyr side

* Interrupts are now synced to instruction lifetimes
* Interrupts are disabled on traps and mie is pushed to mpie
* Zephyr applications regenerated from rewritten Zephyr port
* Timer is 32-bit to avoid wrapping around too often
* MEPC was not read properly from CSR storage
 2019-11-19 11:06:50 +01:00
Olof Kindgren
603c168d9b Allow readback of GPIO signal 2019-11-19 10:46:30 +01:00
Olof Kindgren
ed02951b4d Add vcd_start parameter 2019-11-19 10:46:15 +01:00
Olof Kindgren
40e7855bac Add width and divider parameters to servant_timer 2019-11-19 10:46:03 +01:00
Olof Kindgren
1a961af5ac Only allocate used RF mem 2019-11-10 21:45:34 +01:00
Gwenhael Goavec-Merou
61c8a6b886 add arty_a7_35t support 2019-11-10 21:44:50 +01:00
Gwenhael Goavec-Merou
d90030b955 xilinx PLL: allows to specify PLL output frequency (16 or 32 MHz) 2019-11-10 21:44:50 +01:00
Gwenhael Goavec-Merou
1f6d215d19 README: argument to use blinky example instead of hello world is true for all boards 2019-11-10 15:36:15 +01:00
Gwenhael Goavec-Merou
cf187bc81e README: --firmware parameter only available for sim and verilator_tb targets 2019-11-07 09:05:33 +01:00
Fabien Marteau
529cf6192b path correction and little comment (#12) 
* path fixed

* Update README.md

Little comment to says that simulation should be stopped with Ctrl-C.

* Update README.md

adding dependencies

* Update README.md
 2019-11-05 10:04:59 +01:00
Olof Kindgren
9c83e39635 Initialize state of verilator UART decoder 2019-11-04 13:01:31 +01:00
Olof Kindgren
98bfcc3b62 Remove unused jalr signal 2019-10-30 09:07:58 +01:00
Olof Kindgren
75decc8251 Bring back old immediate decoder 
This was originally thrown out since it was slow and cost too much
resources. Due to other changes in the core, it is now cheaper
than the other one
 2019-10-29 21:54:22 +01:00
Olof Kindgren
ab39209773 Move servant arbiter below dbus mux 2019-10-29 21:53:13 +01:00
Olof Kindgren
72e34ce795 Simplify servant_arbiter 2019-10-29 21:53:13 +01:00
Olof Kindgren
4f32975989 Consistent naming of servant components 2019-10-29 21:53:13 +01:00
Olof Kindgren
9b5401811e servant: Only ignore memfile for verilator 2019-10-29 21:53:13 +01:00
Olof Kindgren
57b4fca05f Ignore initial garbage in verilator UART decoder 2019-10-29 21:53:13 +01:00
Olof Kindgren
574464a33b De-pipeline alu_result_sel 2019-10-29 21:53:13 +01:00
Fabien Marteau
b9a9e99e2b Suppressing some verilator lint warnings 2019-10-22 10:53:23 +02:00
Fabien Marteau
e5061ca5f8 Update README.md (#9) 
* Update README.md
 2019-10-22 09:15:35 +02:00
Olof Kindgren
8bc54a99ad Move mcause generation to serv_csr 2019-09-26 23:36:02 +02:00
Olof Kindgren
2b5c71fe9b Gate mem_rd in mem_if 2019-09-26 23:31:23 +02:00
Olof Kindgren
0f767ad2d3 Gate mem_misalign in mem_if 2019-09-26 23:23:42 +02:00
Olof Kindgren
5b96b3a938 Simplify jump flag 2019-09-26 23:12:07 +02:00
Olof Kindgren
7bd89deb41 Simplify mret/csr address generation 2019-09-26 23:09:22 +02:00
Olof Kindgren
126937f16a Rewrite RF and state machine 
Big patch, but would take more work to split it up
 2019-09-26 23:09:22 +02:00
Olof Kindgren
8481fb46a1 Remove dead code 2019-09-26 22:59:46 +02:00
Olof Kindgren
bad823ff6d Fix syntax error for o_take_branch 2019-09-26 22:59:46 +02:00
Olof Kindgren
ca2beaf786 Pass rf_rreq through serv_state 2019-09-26 22:59:46 +02:00
Olof Kindgren
3d6eb3feca Separate rf_ready and dbus_ack 2019-09-26 22:59:46 +02:00
Florian Zaruba
27621a285e rtl: Make compatible to Synopsys Design Compiler 
Synopysis DC has problems with forward references and initial
statements. Fixed that for better compatibility.
 2019-09-26 22:57:40 +02:00
Olof Kindgren
ec6c7a7cd5 Update README 2019-09-16 16:57:56 +02:00
Olof Kindgren
920ad92bc7 Remove unused rs_en signal 2019-09-16 10:45:42 +02:00
Olof Kindgren
6518b5f30f Simplify bufreg_hold 2019-09-16 09:05:47 +02:00
Olof Kindgren
ef7706f26b Simplify two-stage signalling 2019-09-16 09:03:02 +02:00
Olof Kindgren
d4c782bce6 Set o_dbus_we directly from decode 2019-09-16 00:13:21 +02:00
Olof Kindgren
b9e410a0a0 Remove bytepos from serv_mem_if 2019-09-16 00:07:58 +02:00
Olof Kindgren
5a44634ee5 Avoid exposing funct3 from decode 2019-09-15 23:50:02 +02:00
Olof Kindgren
9575eb4fef Separate decode and state 2019-09-15 23:25:10 +02:00
Olof Kindgren
7289a68f6e Separate state from o_bufreg_loop 2019-09-14 22:52:41 +02:00
Olof Kindgren
c0a177aebe Simplify o_alu_cmp_uns 2019-09-14 22:21:25 +02:00