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Author	SHA1	Message	Date
felsabbagh3	d0765b8fb1	Now Flush Routine only sends one round of snoops	2020-04-04 18:02:57 -07:00
felsabbagh3	65fa9285bf	Fixed Flushing and Prefetching	2020-04-04 17:57:35 -07:00
felsabbagh3	a7a1906bea	Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis	2020-04-04 10:14:24 -07:00
felsabbagh3	70bd673031	Resseting GPR	2020-04-04 10:13:26 -07:00
Blaise Tine	0a8d829f15	basic test update	2020-04-04 09:07:04 -04:00
Blaise Tine	07ec0ef344	OPAE hw snooping fixes	2020-04-04 05:07:45 -07:00
Blaise Tine	1f63139ce5	fix RTL code undefined variables	2020-04-03 22:59:40 -07:00
Blaise Tine	41f3245376	enable Vortex compiler to support using environment path	2020-04-03 20:24:57 -04:00
Blaise Tine	5e54bdffe9	POCL compiler with relative path	2020-04-03 17:47:55 -04:00
codetector	621e0b2a25	Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis	2020-04-03 15:06:58 -04:00
Blaise Tine	6ae9a6732b	Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis	2020-04-03 15:04:15 -04:00
codetector	9ee12d4a01	Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis	2020-04-03 14:36:52 -04:00
felsabbagh3	10e445d459	Provisioned Prefetching, currently disabled	2020-04-03 00:30:33 -07:00
Blaise Tine	c05ea79afa	Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis	2020-04-03 00:13:46 -04:00
Blaise Tine	66a879608e	udpated OpenCL runtime to include cache flushing	2020-04-03 00:13:24 -04:00
felsabbagh3	8ad75e0442	Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis	2020-04-02 20:26:46 -07:00
felsabbagh3	7d1cc5234e	Fixed dram_fill_accept dependant on input address	2020-04-02 20:26:37 -07:00
Blaise Tine	ee77c76785	Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis	2020-04-02 20:09:20 -07:00
Blaise Tine	f590d6acc8	minor update	2020-04-02 20:09:08 -07:00
felsabbagh3	8c1b72691f	Updated head location to 9-a	2020-04-02 19:41:53 -07:00
Blaise Tine	fbda21d5f5	Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis	2020-04-02 19:38:49 -07:00
felsabbagh3	478c3cf21d	Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis	2020-04-02 19:19:31 -07:00
felsabbagh3	0e0b326b31	Removed bank Hazard Signals	2020-04-02 19:19:00 -07:00
Blaise Tine	5b9ee0bb7b	Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis	2020-04-02 16:01:52 -07:00
Blaise Tine	bc6b2969ef	minor opae hw fixed	2020-04-02 15:41:12 -07:00
codetector	26b9fef2d8	remove binaries	2020-04-02 14:20:14 -04:00
codetector	00f202bddb	two more benchmarks	2020-04-02 14:16:16 -04:00
codetector	c6319a0dbd	more gitignore update	2020-04-02 14:16:02 -04:00
codetector	b9e5612949	fix gitignore	2020-04-02 14:13:48 -04:00
codetector	abc0624086	fix makefile	2020-04-02 14:13:38 -04:00
codetector	299e3aa72f	kmeans should compile with new loading methid	2020-04-02 14:08:57 -04:00
Blaise Tine	6463cca529	extending basic test	2020-04-02 08:46:32 -07:00
Blaise Tine	efd3c1d154	udpate	2020-04-02 06:51:11 -04:00
Blaise Tine	f7b7c509d5	udpate	2020-04-02 05:16:13 -04:00
Blaise Tine	7e4399e3ac	OPAE HW full redesign - basic test passing	2020-04-02 05:10:51 -04:00
felsabbagh3	7b4b44e5ab	Fixed DRAM random latency simulator	2020-03-31 20:33:45 -07:00
felsabbagh3	1b9d9f3625	Fixed incorrect miss_add on pipeline stall	2020-03-31 20:23:09 -07:00
Blaise Tine	bca5ac5e7f	enable rtl sim dram stalls	2020-03-31 02:41:14 -04:00
Blaise Tine	e92c4b6774	enable rtl sim dram stalls	2020-03-31 02:38:18 -04:00
felsabbagh3	ba8bc95c90	Newlib update	2020-03-30 23:08:38 -07:00
felsabbagh3	bcf894b581	Demo SOC W=8, T=4 Passing	2020-03-30 22:17:38 -07:00
felsabbagh3	66a837b0df	SOC only 2 errors	2020-03-30 21:28:40 -07:00
felsabbagh3	88f2ad53d0	Fixed simulator includes	2020-03-30 16:43:26 -07:00
Blaise Tine	f6eb5dfbae	refactor RTL sim, added DRAM stalls support	2020-03-30 04:13:19 -04:00
felsabbagh3	638625184f	Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis	2020-03-29 23:46:44 -07:00
felsabbagh3	ff2b8dba12	Fixed req_addr width	2020-03-29 23:46:38 -07:00
Blaise Tine	0f39d0fcbd	Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis	2020-03-30 01:53:53 -04:00
Blaise Tine	2eb19e23c2	refactor RTL simulator	2020-03-30 01:53:34 -04:00
felsabbagh3	ccc65a06fe	Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis	2020-03-29 21:22:08 -07:00
felsabbagh3	36895d6e7c	Fixed miss_add on for snoop replays	2020-03-29 21:21:53 -07:00