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Author SHA1 Message Date
Blaise Tine
073173067f adding back build_config target dependency 2020-03-27 12:41:03 -04:00
Blaise Tine
8763adf7bc update 2020-03-26 04:19:53 -04:00
Blaise Tine
50829e522b update 2020-03-26 04:19:53 -04:00
Blaise Tine
a82dd9387d refactoring RTL simulator and Makefile 2020-03-26 04:14:36 -04:00
Blaise Tine
3252d52694 refactoring RTL simulator and Makefile 2020-03-26 04:14:36 -04:00
wgulian3
3b74f071a7 Generate define overrides based on env vars for C and Verilog. 
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
 2020-03-26 04:08:43 -04:00
wgulian3
f126a23114 Generate define overrides based on env vars for C and Verilog. 
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
 2020-03-26 04:08:43 -04:00
wgulian3
33d8c507df Remove VX_define.h and *_synth and runtime/config.h 2020-03-26 04:07:17 -04:00
wgulian3
123fb17723 Remove VX_define.h and *_synth and runtime/config.h 2020-03-26 04:07:17 -04:00
Blaise Tine
8fd742edd8 fixed Modelsim build errors 2020-03-26 03:56:44 -04:00
Blaise Tine
acafcceb94 fixed Modelsim build errors 2020-03-26 03:56:44 -04:00
Blaise Tine
9621acff5b fixed Modelsim build errors 2020-03-26 03:54:23 -04:00
Blaise Tine
8aa2d74714 fixed Modelsim build errors 2020-03-26 03:54:23 -04:00
Blaise Tine
a7eb9a0c38 code refactoring 2020-03-26 03:20:46 -04:00
Blaise Tine
07c52d8729 code refactoring 2020-03-26 03:20:46 -04:00
Blaise Tine
4626389ee2 code refactoring 2020-03-26 01:41:01 -04:00
Blaise Tine
bf3d1fb5a2 code refactoring 2020-03-26 01:41:01 -04:00
felsabbagh3
4e6de0dc38 Fixed most of the cache issues, mat_add left 2020-03-22 15:59:45 -07:00
felsabbagh3
5372c07b01 Fixed most of the cache issues, mat_add left 2020-03-22 15:59:45 -07:00
felsabbagh3
d146070275 Fix for Single-Threaded 2020-03-22 14:44:46 -07:00
felsabbagh3
82ea79c680 Fix for Single-Threaded 2020-03-22 14:44:46 -07:00
wgulian3
902aa685b1 Add threaded -O3 build mode 2020-03-21 17:23:40 -04:00
wgulian3
10ebfd7e24 Add threaded -O3 build mode 2020-03-21 17:23:40 -04:00
wgulian3
1c82f9a11d revert saxpy change and fix stage_1_cycles not working 2020-03-20 04:49:02 -04:00
wgulian3
f565d47844 revert saxpy change and fix stage_1_cycles not working 2020-03-20 04:49:02 -04:00
wgulian3
05b7ffff12 Add modified RTL files for parameterized builds with VX_define_synth.v 2020-03-20 04:04:15 -04:00
wgulian3
5b3df797a4 Add modified RTL files for parameterized builds with VX_define_synth.v 2020-03-20 04:04:15 -04:00
Blaise Tine
f034b4c63a driver update 2020-03-16 18:13:58 -04:00
Blaise Tine
55e2cb4a76 driver test kernel 2020-03-16 17:49:24 -04:00
Blaise Tine
8b4397f0ec fixed runtime Makefile 2020-03-16 14:58:02 -04:00
Blaise Tine
db87f0184b added driver sim 2020-03-16 08:02:57 -04:00
Blaise Tine
c41855ee42 added driver sim 2020-03-16 08:02:23 -04:00
felsabbagh3
65f3ced608 Fixed no L3 Verilator issues 2020-03-13 15:11:20 -07:00
felsabbagh3
ff2fc5fa43 Fixed no L3 Verilator issues 2020-03-13 15:11:20 -07:00
felsabbagh3
fc94168e32 Removed L3 for synthesis 2020-03-13 15:01:46 -07:00
felsabbagh3
0f5528a229 Removed L3 for synthesis 2020-03-13 15:01:46 -07:00
wgulian3
dd2c9cd9d7 Add power analysis Make target 2020-03-12 13:14:50 -04:00
wgulian3
07ed4085ae Add power analysis Make target 2020-03-12 13:14:50 -04:00
wgulian3
b1e77bec44 replace procedural continuous assignments and force MLAB inference for generic_queue_ll 2020-03-10 17:46:48 -04:00
wgulian3
c5fe43724e replace procedural continuous assignments and force MLAB inference for generic_queue_ll 2020-03-10 17:46:48 -04:00
wgulian3
372a1ad905 minor tweaks to appease quartus 
re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
 2020-03-10 12:15:30 -04:00
wgulian3
a931b588c2 minor tweaks to appease quartus 
re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
 2020-03-10 12:15:30 -04:00
felsabbagh3
13c6cbfa5d L3 and CLUSTRING WORKS 2020-03-10 02:41:47 -07:00
felsabbagh3
ca62e57a0d L3 and CLUSTRING WORKS 2020-03-10 02:41:47 -07:00
felsabbagh3
cf0173ae15 Fixed Stall Pipeline Logic 2020-03-09 22:08:46 -07:00
felsabbagh3
dea271eb6b Fixed Stall Pipeline Logic 2020-03-09 22:08:46 -07:00
Blaise Tine
36547821fc temp files cleanup 2020-03-09 10:18:11 -04:00
Blaise Tine
717a75ade8 fixed opencl benchmarks 2020-03-09 09:55:16 -04:00
felsabbagh3
e2ffbcf14b MULTICORE WITH L2 WORKING 2020-03-09 01:17:11 -07:00
felsabbagh3
469334f23e MULTICORE WITH L2 WORKING 2020-03-09 01:17:11 -07:00