225 commits

Author	SHA1	Message	Date
Blaise Tine	7560202f8b	cache bank refactoring - removing unecessary core response fifo & restoring single port data access	2021-02-21 21:47:46 -08:00
Blaise Tine	3e961c4e6e	minor update	2021-02-21 15:14:46 -08:00
Blaise Tine	6739dc7923	minor update - registering execute units skid buffers	2021-02-21 15:11:08 -08:00
Blaise Tine	258eb633a6	minor update	2021-02-20 13:16:25 -08:00
Blaise Tine	05f93fac20	minor update	2021-02-20 13:15:15 -08:00
Blaise Tine	31b3e380dc	minor update	2021-02-15 09:23:40 -08:00
Blaise Tine	073964fdf7	minor update	2021-02-12 08:52:06 -08:00
Blaise Tine	ab63ac9e5d	cache request interfaces update	2021-02-10 20:55:04 -08:00
Blaise Tine	665b97b810	multi-ported cache support for streaming	2021-02-08 16:13:32 -08:00
Blaise Tine	fd1726197b	cache merge optimization	2021-02-07 07:33:39 -08:00
Blaise Tine	72b6713a72	updating fdiv/fsqrt bram hex files, reset_delay updaet	2021-02-04 09:02:18 -08:00
Blaise Tine	de2e118cc2	move opae to /hw/syn/	2021-01-25 02:32:49 -08:00
Blaise Tine	8775f63ec4	lkg build rollout with 16cores optimization on arria10	2021-01-24 16:49:22 -08:00
Blaise Tine	74a687e395	minor updates	2021-01-18 05:43:30 -08:00
Blaise Tine	a69ba5ad7b	cache flush support	2021-01-17 05:50:29 -08:00
Blaise Tine	d4e7b28be8	cache refactoring	2021-01-17 00:18:56 -08:00
Blaise Tine	e770824d47	fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance	2021-01-10 20:26:15 -08:00
Blaise Tine	146c285aa0	minor update	2021-01-06 19:59:04 -08:00
Blaise Tine	2058718f0f	minor updates	2021-01-06 07:18:14 -08:00
Blaise Tine	31ff70fd4e	minor updates	2021-01-05 15:03:41 -08:00
Blaise Tine	d44144f72f	FPU float<->int conversion optimization	2020-12-29 15:37:45 -08:00
Blaise Tine	25df233005	Adding Altera Stratix 10 support	2020-12-27 10:44:57 -08:00
Blaise Tine	4b7d871d62	allowing partial cache request submissions, io bus support broken	2020-12-21 03:53:13 -08:00
Blaise Tine	4bbd7bf408	performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,	2020-12-19 02:45:06 -08:00
Blaise Tine	e0905f8352	minor update	2020-12-09 05:34:27 -08:00
Blaise Tine	14baec86d5	moved apae sources into rtl/afu	2020-12-08 04:59:11 -08:00
Blaise Tine	d68b32cd60	minor update	2020-12-06 22:40:27 -08:00
Blaise Tine	c3ec4c9e90	minor update	2020-12-03 09:30:59 -08:00
Blaise Tine	f68af3bb84	using mshr pending request size	2020-12-01 00:54:25 -08:00
Blaise Tine	97739e9dcf	RAM blocks inference fixes	2020-11-30 14:02:47 -08:00
Blaise Tine	e6466b887c	minor update	2020-10-20 08:45:21 -07:00
Blaise Tine	7529f72c5d	fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags	2020-10-20 05:32:55 -07:00
Blaise Tine	32da50816f	scope refactoring: adding modules definitions to VCD trace	2020-10-12 23:26:02 -04:00
Blaise Tine	0a45a8beb3	minor update	2020-09-01 00:56:10 -07:00
Blaise Tine	fde3f46798	ibuffer optimization	2020-08-26 04:44:36 -07:00
Blaise Tine	f292e5003d	quartus build fixes	2020-08-23 22:04:46 -07:00
Blaise Tine	1c9445745f	fp_noncomp fixes	2020-08-23 16:53:28 -07:00
Blaise Tine	0b355f228e	ibuffer addition	2020-08-22 00:22:04 -07:00
Blaise Tine	6c12391338	pipeline refactoring - fmax >= 222 mhz	2020-08-14 21:50:14 -07:00
Blaise Tine	cd29362d10	fixed FPU handshake, optimized writeback's critical path	2020-08-07 10:11:54 -07:00
Blaise Tine	ffd9515881	added altera fpu modules	2020-08-05 15:53:59 -07:00
Blaise Tine	836a735555	minor updates	2020-07-31 13:39:52 -07:00
Blaise Tine	c2dd0a8b39	modelsim fixes && pipeline optimization	2020-07-28 14:20:23 -07:00
Blaise Tine	8976100025	floating point support fixes	2020-07-28 04:19:46 -04:00
Blaise Tine	ff7f65bd1f	opae build fixes	2020-07-21 05:44:13 -07:00
Blaise Tine	bdfacf709c	yosys synthesis refactoring	2020-07-10 18:56:41 -04:00
Blaise Tine	f66c251309	minor update	2020-06-29 15:09:14 -07:00
Blaise Tine	f0046fed3c	added synthesis for Vortex single core	2020-06-29 08:39:57 -07:00
Blaise Tine	a70562d386	set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18	2020-06-29 08:03:19 -07:00
Blaise Tine	21e04a0cb0	minor update	2020-06-28 22:58:18 -07:00