43 commits

Author	SHA1	Message	Date
Blaise Tine	a06812f93f	minor updates	2022-02-01 22:51:33 -05:00
Blaise Tine	bf72800676	debug tracing refactoring	2021-10-17 13:42:16 -07:00
Blaise Tine	e380ded5e1	Merge branch 'master' into graphics	2021-10-15 19:32:11 -07:00
Blaise Tine	9f34b2944c	code refactoring for Vivado, sv2v, and yosys compatibility	2021-09-27 08:55:10 -04:00
Blaise Tine	bb1ceffadd	rebase master update	2021-07-30 21:03:14 -07:00
Blaise Tine	2372067817	minor update	2021-06-22 09:30:36 -07:00
Blaise Tine	8543e3a8bf	code refactoring	2021-04-26 02:34:21 -07:00
Blaise Tine	8410c49f53	code refactoring: DRAM => MEM renaming	2021-04-26 00:58:48 -07:00
Blaise Tine	66ea340d05	Fix RAM memory deallocation	2021-03-09 01:52:56 -08:00
Blaise Tine	6c1dc96626	simX refactoring + removed oldRTL + CSR updates	2021-02-06 12:52:54 -08:00
Blaise Tine	ed216ab39d	minor updates	2021-01-17 13:58:43 -08:00
Blaise Tine	2d69ca5d67	scratchpad optimization for stack access using custom bank offset aligned to stack size	2021-01-02 16:00:00 -05:00
Blaise Tine	d44144f72f	FPU float<->int conversion optimization	2020-12-29 15:37:45 -08:00
Blaise Tine	b85391389b	rename MSRQ to MSHR	2020-11-28 17:32:00 -05:00
Blaise Tine	5d58bf3d11	fixed l3cache hang using memory arbiter in afu	2020-11-15 06:36:32 -08:00
Blaise Tine	d2bc820909	Merge branch 'master' of https://github.com/vortexgpgpu/vortex-dev	2020-11-10 14:01:58 -05:00
trmontgomery	e6a8df7be1	miss vec is displayed	2020-11-02 12:01:03 -05:00
Blaise Tine	5be1d85648	cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count	2020-11-02 01:50:12 -08:00
Carter Rene Montgomery	9b7187441d	updated from GT repo	2020-09-08 18:35:47 -04:00
Blaise Tine	6c12391338	pipeline refactoring - fmax >= 222 mhz	2020-08-14 21:50:14 -07:00
Blaise Tine	31ee824862	merged fpu_port branch	2020-07-31 17:13:22 -04:00
Blaise Tine	4bdab8903e	merge	2020-07-31 16:49:59 -04:00
Blaise Tine	27e95530ef	pipeline optimization	2020-07-30 03:06:01 -07:00
Blaise Tine	25f66e6490	pipeline refactoring	2020-07-19 05:03:47 -04:00
trmontgomery	340dd683eb	cleanup	2020-07-19 00:37:06 -04:00
trmontgomery	3e8179f37f	added assert_equal to read/write test	2020-07-19 00:34:44 -04:00
trmontgomery	ed3a0cfa4d	added rsp map	2020-07-19 00:08:09 -04:00
trmontgomery	2d39e0561c	Revert "successfully invalidate req after empty" ... This reverts commit 9ed2012b12.	2020-07-18 23:58:56 -04:00
trmontgomery	9ed2012b12	successfully invalidate req after empty	2020-07-18 19:54:43 -04:00
trmontgomery	8ffc65f22f	read/write test works with core_req_t	2020-07-18 19:25:03 -04:00
trmontgomery	2fc65f4a7d	clear req after sending	2020-07-13 23:54:33 -04:00
trmontgomery	172e6d09af	read and write complete	2020-07-13 23:51:26 -04:00
trmontgomery	0e8b9ec1c2	read and write complete	2020-07-13 23:48:51 -04:00
trmontgomery	e155c8a9b3	cache makfile changes	2020-06-30 22:40:14 -04:00
trmontgomery	9f33a9feb7	cache_sim.cpp created	2020-06-30 17:49:43 -04:00
Blaise Tine	8302641510	fpga fixes	2020-06-27 14:03:20 -07:00
Blaise Tine	de9fc68ccc	opae fixes	2020-05-06 21:14:53 -07:00
Blaise Tine	ba4e736782	RTL code refactoring	2020-04-21 01:03:37 -04:00
Blaise Tine	8e7046a388	RTL code refactoring	2020-04-20 14:05:08 -04:00
Blaise Tine	1a2823da0d	RTL code refactoring	2020-04-20 13:52:24 -04:00
Blaise Tine	a0e15af0dc	RTL code refactoring	2020-04-20 13:01:42 -04:00
Blaise Tine	12dc4d6874	refactoring fixes	2020-04-14 19:39:59 -04:00
Blaise Tine	fc155e1223	project directories reorganization	2020-04-14 06:35:20 -04:00