973 commits

Author	SHA1	Message	Date
Jaewon Lee	0bf79a0f05	Revert "Initial HBM changes for RTL"	2024-10-04 10:13:31 -04:00
sij814	e8ce3878bb	Merge branch 'master' of github.com:vortexgpgpu/vortex	2024-09-19 13:36:46 -07:00
sij814	4fff940e42	two different versions of bypass connection	2024-09-19 13:21:14 -07:00
sij814	48f86a48f6	changed mem_req_arb in VX_cache_l3.sv to accept data_out	2024-09-18 22:05:40 -07:00
sij814	992f8d97d3	sliced the bypass requests	2024-09-17 19:47:13 -07:00
jaewon-lee-github	daec55ae95	change the ci version	2024-09-12 11:24:37 -04:00
Jaewon Lee	e91eb4aed4	merge from master branch	2024-09-12 10:32:02 -04:00
Hanran Wu	ea9560b33b	merge	2024-08-23 17:44:24 -04:00
sij814	7ae7ffa007	pulled master and made initial changes	2024-08-22 18:37:34 +02:00
sij814	ea34239b43	changes made for initial feedback	2024-08-13 16:52:27 -07:00
sij814	de81baaabf	hbm for vortex 2.2	2024-08-12 02:52:47 -07:00
Blaise Tine	c265ff97b8	minor updates	2024-08-06 12:58:58 -07:00
Blaise Tine	d276875ab9	fixed memory block size configuration	2024-08-06 12:47:05 -07:00
Blaise Tine	50b12ef754	fixed memory block size configuration	2024-08-06 12:46:19 -07:00
Blaise Tine	0096e60f03	Making LUT optimization optional	2024-08-06 12:38:30 -07:00
Blaise Tine	9dcb377b67	Moving from one-hot to binary muxing optimization ... FPGA synthesis is suboptimal with one-hot muxing, particularly Xilinx Vivado. This change fixed Xilinx synthesis for 256-thread cores.	2024-08-06 12:32:02 -07:00
Blaise Tine	b81ae8e431	reset network cleanup	2024-08-04 22:50:28 -07:00
Blaise Tine	42c62001ec	fair arbiter speed optimization	2024-08-04 22:13:47 -07:00
Blaise Tine	74579fd4dc	minor update	2024-08-04 14:13:26 -07:00
Blaise Tine	cb1e49d3f6	minor update	2024-08-03 17:08:16 -07:00
Blaise Tine	4b6a48c716	minor update	2024-08-03 13:37:01 -07:00
Blaise Tine	07981a585c	minor update	2024-08-03 13:00:34 -07:00
Blaise Tine	4b93c9ffb5	minor updates	2024-08-03 11:49:12 -07:00
Blaise Tine	35fb50f9a6	minor updates	2024-08-03 10:43:08 -07:00
Blaise Tine	4c1b3fd88d	local memory area optimization	2024-08-03 00:10:06 -07:00
Blaise Tine	52c5f1ff6b	minor update	2024-08-02 23:32:34 -07:00
Blaise Tine	76f74b8a59	minor update	2024-08-02 19:50:34 -07:00
Blaise Tine	e8cdae1225	minor fix in VX_local_mem.sv	2024-08-02 19:19:57 -07:00
Blaise Tine	067b7a8726	fixed typo	2024-08-02 18:57:07 -07:00
Blaise Tine	410c47e2ae	adding out_buf to VX_pe_serializer + testing	2024-08-02 18:16:50 -07:00
Blaise Tine	f723e7baf5	registering local memory bram output	2024-08-02 18:15:08 -07:00
Blaise Tine	9c5aee5e25	bram reset fix	2024-08-02 18:13:58 -07:00
Blaise Tine	c1b8ecfd1a	block ram reset refactoring	2024-08-02 16:39:40 -07:00
Blaise Tine	16c209ac0c	fixed operand collector critical path	2024-08-02 16:23:36 -07:00
Blaise Tine	3075c1737b	fixed bug in VX_onehot_encoder.sv (see issue #126)	2024-08-02 15:12:10 -07:00
Blaise Tine	29c5a28273	minor update	2024-08-02 00:36:10 -07:00
Blaise Tine	e53b295eea	writeback cache fixes	2024-07-31 20:53:40 -07:00
Blaise Tine	81251b1af8	minor update	2024-07-31 13:55:44 -07:00
Blaise Tine	ef5d58dc9e	cache regression tests	2024-07-31 11:45:51 -07:00
Blaise Tine	4dc34cfd2d	hw arbitration update	2024-07-31 10:52:57 -07:00
Blaise Tine	3fe8f963aa	writeback cache fixes	2024-07-31 02:20:32 -07:00
Blaise Tine	516ce43a5c	testing writeback cache	2024-07-30 22:21:10 -07:00
Blaise Tine	2e77c9eec2	writeback cache fixes	2024-07-30 22:14:06 -07:00
Blaise Tine	95ca49a85f	writeback cache fixes	2024-07-30 20:38:06 -07:00
Blaise Tine	e1c5b5277e	minor update	2024-07-30 17:55:21 -07:00
Blaise Tine	abf8d2c51a	minor update	2024-07-30 05:59:50 -07:00
Blaise Tine	6e55840a32	minor update	2024-07-30 03:32:49 -07:00
Blaise Tine	047960ac4d	minor update	2024-07-30 02:51:12 -07:00
Blaise Tine	f46b764748	minor update	2024-07-30 01:59:50 -07:00
Blaise Tine	99cbae1820	writeback cache deadlock fix	2024-07-30 01:55:32 -07:00