973 commits

Author	SHA1	Message	Date
Blaise Tine	f84c8a0b5d	instr_sched => ibuffer	2021-06-27 19:36:43 -07:00
Blaise Tine	1ea738ed26	lkg build	2021-06-25 16:28:10 -07:00
Blaise Tine	7e0dc81cee	minor update	2021-06-23 04:19:13 -07:00
Blaise Tine	1a33c83e6e	minor update	2021-06-23 04:17:45 -07:00
Blaise Tine	a3a7239b4d	critical path optimizations	2021-06-23 01:51:23 -07:00
Blaise Tine	b8fd2308e1	arbiter specialization	2021-06-22 21:02:37 -07:00
Blaise Tine	d7bce5ab45	relaxing fcvt critical path	2021-06-22 09:34:35 -07:00
Blaise Tine	2372067817	minor update	2021-06-22 09:30:36 -07:00
Blaise Tine	c331da5ff7	adding fast DPI implemntation of imul and idiv	2021-06-22 09:02:41 -07:00
Blaise Tine	65a3704479	minor update	2021-06-18 01:18:31 -07:00
Blaise Tine	57143f5889	synthesis optimizations	2021-06-17 16:43:43 -07:00
Blaise Tine	288f0c976b	fix split/join hardware	2021-06-15 16:06:54 -04:00
Blaise Tine	6213b1a910	vortex runtime console out implementation	2021-06-15 04:01:44 -04:00
Blaise Tine	ee06337553	duplicate addressing fix	2021-06-14 05:53:18 -04:00
Blaise Tine	fe86fd7936	xMerge branch 'master' of https://github.gatech.edu/casl/Vortex	2021-06-13 21:44:46 -04:00
Blaise Tine	03406c0a3f	project tests refactoring	2021-06-13 17:42:04 -07:00
Blaise Tine	47c3234659	minor update	2021-06-13 10:58:48 -07:00
Blaise Tine	76c4909ae9	minor update	2021-06-12 02:22:01 -04:00
Blaise Tine	3cc1190cd7	CSRs I/O refactoring	2021-06-11 03:08:07 -07:00
Blaise Tine	a46d6cb606	ebreak workaround for RISC-V tests	2021-06-10 19:55:33 -07:00
Blaise Tine	e234204e0c	Merge branch 'staging' of https://github.com/vortexgpgpu/vortex	2021-06-10 19:54:01 -07:00
Blaise Tine	8bf85c1983	fixed non-cacheable memory with l2 cache	2021-06-10 15:11:37 -07:00
Blaise Tine	cbca7e12c6	removing ebreak signals from public interface	2021-06-10 12:57:44 -07:00
Blaise Tine	adf033b0aa	non-cacheable memory address critical paths optimizations	2021-06-10 12:47:18 -07:00
Blaise Tine	41069ba188	non-cacheable memory address fixes	2021-06-06 20:54:36 -07:00
Blaise Tine	3071fb7a29	adding support for non-cacheable memory addressing	2021-06-06 13:35:55 -07:00
Blaise Tine	5d2437d887	refactoring cache_config	2021-05-27 14:41:46 -07:00
Blaise Tine	4c5104e96a	fixed shared memory multi-tag requests bug	2021-05-26 15:03:48 -07:00
Blaise Tine	d8517d4d08	minor update	2021-05-26 13:37:07 -07:00
Blaise Tine	c7f85b76ed	minor update	2021-05-26 13:36:10 -07:00
Blaise Tine	093008fa1e	minor update	2021-05-25 09:13:32 -07:00
Blaise Tine	6388d87ec5	afu bug fix	2021-05-24 18:06:11 -07:00
Blaise Tine	244f4b0964	fixed shared memory write bug	2021-05-23 10:57:58 -07:00
Blaise Tine	d3f0a77ae5	fixed databus arbiter bug	2021-05-23 10:57:02 -07:00
Blaise Tine	d80e1b28a3	fixes for multi-channel memory support	2021-05-20 05:36:09 -07:00
Blaise Tine	7095a46066	minor update	2021-05-18 11:15:36 -07:00
Blaise Tine	3e88a71801	minor update	2021-05-06 08:55:46 -07:00
Blaise Tine	6107bf8247	minor fix	2021-05-04 11:05:07 -07:00
Blaise Tine	8f451aa74c	minor update	2021-05-04 08:01:49 -07:00
Blaise Tine	bde6a69ea0	adding support for multi-banks memory bus	2021-05-04 07:32:03 -07:00
Blaise Tine	228aee1ec7	lsu_unit pending queue bug fix	2021-05-03 12:25:44 -07:00
Blaise Tine	bac53e4ae1	minor update	2021-05-02 11:05:49 -07:00
Blaise Tine	04a1c0e9eb	IN_ORDER_MEM feature doesn't work becasue when cache bank's mem-req-queue is full, we need to schedule the mem response and skip the mshr	2021-05-01 13:44:08 -07:00
Blaise Tine	e40a3feefa	minor update	2021-05-01 10:33:24 -07:00
Blaise Tine	d504adb236	afu mem controller refactoring	2021-05-01 08:39:52 -07:00
Blaise Tine	95f057bc2e	fpga build refactoring	2021-04-29 06:17:28 -07:00
Blaise Tine	64848788a1	minor update	2021-04-26 20:34:28 -07:00
Blaise Tine	8543e3a8bf	code refactoring	2021-04-26 02:34:21 -07:00
Blaise Tine	8410c49f53	code refactoring: DRAM => MEM renaming	2021-04-26 00:58:48 -07:00
Blaise Tine	d808aa2735	perf counters generic size	2021-04-25 21:15:24 -07:00