973 commits

Author	SHA1	Message	Date
Blaise Tine	a60361ac2d	minor update	2021-04-25 21:10:54 -07:00
Blaise Tine	cad21a4b92	minor update	2021-04-24 01:17:38 -04:00
Blaise Tine	4cb98a25a7	enabling 128-bit dram bus	2021-04-24 00:31:27 -04:00
Blaise Tine	aff5903a22	minor ibuffer critical path optimization.	2021-04-19 20:53:13 -07:00
Blaise Tine	625689796f	minor update	2021-04-04 23:42:57 -07:00
Blaise Tine	2ce6dbb495	minor update	2021-04-04 17:57:35 -07:00
Blaise Tine	5cfd6e6f82	minor updates	2021-04-04 04:04:41 -07:00
Blaise Tine	d522611ee2	minor update	2021-04-03 05:07:00 -07:00
Blaise Tine	d6552a8851	minor update	2021-04-03 04:24:37 -07:00
Blaise Tine	f829bd3c18	minor update	2021-04-03 04:22:44 -07:00
Blaise Tine	1e2da696ce	arrays logging	2021-04-02 02:20:15 -07:00
Blaise Tine	a75accf6ed	minor update	2021-04-01 23:31:55 -07:00
Blaise Tine	638614fd6d	decode optimization	2021-04-01 19:08:15 -07:00
Blaise Tine	04a96e89c9	minor update	2021-04-01 12:34:18 -07:00
Blaise Tine	a194521683	minor update	2021-03-31 02:37:16 -07:00
Blaise Tine	d15e33e87f	fpu dpi update	2021-03-31 02:36:34 -07:00
Blaise Tine	b3167d763b	minor update	2021-03-30 22:08:26 -07:00
Blaise Tine	16bef8937b	adding empty to index_buffer	2021-03-30 10:15:42 -07:00
Blaise Tine	b33a994f49	minor update	2021-03-29 23:51:05 -07:00
Blaise Tine	fc70bb3a4a	databus optimization	2021-03-29 23:48:04 -07:00
Blaise Tine	8d4e2e7f70	minor update	2021-03-22 23:04:54 -07:00
Blaise Tine	09dbeacc14	minor update	2021-03-22 23:04:35 -07:00
Blaise Tine	af1bb33557	minor update	2021-03-21 16:38:53 -07:00
Blaise Tine	bd40e7db70	minor update - mux reordering to reduce critical path on input data	2021-03-21 11:43:57 -07:00
Blaise Tine	f7d6b71ac2	minor update	2021-03-21 11:40:54 -07:00
Blaise Tine	09194a8501	minor update	2021-03-21 11:39:33 -07:00
Blaise Tine	e85fa9d842	fixed FCVT timing critical path	2021-03-18 13:26:36 -07:00
Blaise Tine	a79253329c	relaxing commit back-pressure in writeback stage	2021-03-15 14:39:55 -07:00
Blaise Tine	10a994d11a	csr minor update	2021-03-08 03:46:07 -08:00
Blaise Tine	062d02ddce	Merge branch 'master' of https://github.gatech.edu/casl/Vortex	2021-03-04 20:51:03 -08:00
Blaise Tine	8a86bddd3e	fixed simX multicore support, added shared memory	2021-03-04 20:45:27 -08:00
Blaise Tine	5e3a949d2d	floating-point conversion fix	2021-03-01 06:11:03 -08:00
Blaise Tine	b023496ecb	minor update	2021-03-01 03:00:58 -08:00
Blaise Tine	ad06408044	minor update	2021-03-01 01:51:25 -08:00
Blaise Tine	0e3872ee94	floating-point CSR fix	2021-03-01 01:46:41 -08:00
Blaise Tine	b441870789	rename use_imm and use_PC	2021-03-01 00:38:46 -08:00
Blaise Tine	e3a11e4a5c	minor fix	2021-02-28 14:18:43 -08:00
Blaise Tine	3f5fd6d394	using shiftreg-based skid buffers	2021-02-28 02:20:09 -08:00
Blaise Tine	e64996946d	using 44-bit perf counters - aligned with DSP counters width	2021-02-28 02:05:47 -08:00
Blaise Tine	8a9a67aa5a	minor update	2021-02-27 21:54:55 -08:00
Blaise Tine	f5a17bd1a9	decode optimization and refactoring	2021-02-27 18:21:41 -08:00
Blaise Tine	ebee332e9d	minor update	2021-02-27 02:31:05 -08:00
Blaise Tine	20d704b4d3	skid buffer optimization	2021-02-27 02:29:48 -08:00
Blaise Tine	34ce0b8e89	minor update	2021-02-23 20:54:03 -08:00
Blaise Tine	700f9eea19	moving MUL unit into ALU unit	2021-02-23 13:49:02 -08:00
Blaise Tine	1792571e1b	minor update	2021-02-22 13:30:45 -08:00
Blaise Tine	1346d64ba9	minor update	2021-02-22 04:04:13 -08:00
Blaise Tine	7560202f8b	cache bank refactoring - removing unecessary core response fifo & restoring single port data access	2021-02-21 21:47:46 -08:00
Blaise Tine	ccb74ef286	cache data access with decoupled read/write ports	2021-02-21 15:18:24 -08:00
Blaise Tine	6739dc7923	minor update - registering execute units skid buffers	2021-02-21 15:11:08 -08:00