266 commits

Author	SHA1	Message	Date
Blaise Tine	69126dfd35	SimX writeback configuration	2024-07-27 17:25:13 -07:00
Blaise Tine	904a6dc136	fixed trace format consistency	2024-07-27 17:24:14 -07:00
Blaise Tine	c8455eb562	minor update	2024-07-27 01:35:07 -07:00
Blaise Tine	3de14dd8bf	Verilator crash workaround	2024-07-24 16:09:27 -07:00
Blaise Tine	2773b87ae5	minor update	2024-07-24 15:38:49 -07:00
Blaise Tine	c5c4ccdd95	CI workflow optimization	2024-07-23 13:15:34 -07:00
Blaise Tine	b3a4d58825	fixed lsu stats	2024-07-23 13:13:51 -07:00
Blaise Tine	99f114aba3	minor updates	2024-07-23 13:13:24 -07:00
Blaise Tine	eb92e0bdbe	fixed simx lsu-unit bug	2024-07-23 11:29:56 -07:00
Blaise Tine	60f7786e17	BitVector class bug fixes	2024-07-23 09:40:20 -07:00
Blaise Tine	95f59d23a8	simx memory coalescer bug fix	2024-07-23 00:02:43 -07:00
Blaise Tine	24e8e91a94	DramSim fix	2024-07-22 03:37:10 -07:00
Blaise Tine	527910b31e	regression fixes	2024-07-22 00:29:56 -07:00
Blaise Tine	a5377d78ca	minor update	2024-07-21 14:50:59 -07:00
Blaise Tine	fb141ae522	Ramulator 2.0 with HBM 2.0 support ... Verilator 5.0 support SimX C++17 requirement	2024-07-21 06:57:13 -07:00
Blaise Tine	578c3d33d2	cumulative fixes	2024-07-15 10:13:57 -07:00
Blaise Tine	0dbcddcb54	minor update	2024-07-14 03:12:30 -07:00
Blaise Tine	a2307a28dc	perf counters update	2024-07-12 19:02:43 -07:00
Blaise Tine	42f3d55e15	SimX operands collector optimization	2024-07-12 04:54:44 -07:00
Blaise Tine	3efced37c5	trace INSTANCE_ID refactoring	2024-07-09 13:33:17 -07:00
Jaewon Lee	c13e02b19f	Change STARTUP_ADDR from 0x40000000 to 0x80000000(32b) and 0x180000000(64b)	2024-06-30 03:10:36 -04:00
Jaewon Lee	ccbb2243cc	fixed compile error	2024-06-30 00:54:22 -04:00
Jaewon Lee	3caeeeea13	satp_ is not set, then we skip VAT	2024-06-30 00:35:26 -04:00
Jaewon Lee	d531fa6b26	64bit support	2024-06-29 17:43:20 -04:00
Blaise Tine	934416d3ec	debug scope environment fix	2024-06-28 07:55:58 -07:00
Nayan Sivakumar Nair	5b0fc8cbd4	Fixes for PR	2024-06-25 03:18:50 -04:00
Jaewon Lee	02091f3d44	Merge Vortex 2.2	2024-06-22 23:55:01 -04:00
Nayan Sivakumar Nair	a378aed67c	Moved tc_num, tc_size param to makefile args	2024-06-21 22:23:24 -04:00
Blaise Tine	deee7cd8b0	fixed tracing support for xilinx simulation	2024-06-18 23:11:58 -07:00
Jaewon Lee	862997fc94	Virtual Memory Support	2024-06-19 01:52:22 -04:00
Jaewon Lee	62673b4b72	Update upload and download function in simx runtime	2024-06-19 01:43:11 -04:00
Jaewon Lee	01c7b5e384	Change the declaration of set_processor_satp function	2024-06-19 01:36:26 -04:00
Jaewon Lee	cfcece940e	Merge Austin's code (Preliminary)	2024-06-19 01:36:26 -04:00
Hanran Wu	2b426693f5	expand MemoryUnit class defs and add some tlb-related functions	2024-06-19 01:09:56 -04:00
Varsha Singhania	0e3badf723	Script checkin and code cleanup	2024-06-18 02:19:57 -04:00
Varsha Singhania	99c6a1af5a	Tensor cores in Vortex	2024-06-17 04:28:51 -04:00
Blaise Tine	5bcf24ed55	64-bit rtl fix	2024-06-13 06:26:45 -07:00
Blaise Tine	e38187acb5	minor update	2024-06-08 02:47:31 -07:00
Blaise Tine	99eaaf6189	uuid_gen cleanup	2024-06-08 01:57:38 -07:00
Blaise Tine	6c56edf65d	minor update	2024-06-04 14:28:30 -07:00
Blaise Tine	68d2ac6f5e	32-bit/64-bit address space compatibility	2024-05-28 22:30:59 -07:00
Blaise Tine	f8ef570778	riscv tests refactoring	2024-05-28 10:46:31 -07:00
Blaise Tine	47d578c4d2	runtime refactoring	2024-05-27 18:55:42 -07:00
Blaise Tine	32f39264ef	runtime dynamic loading for driver-specific implementations	2024-05-26 19:05:17 -07:00
Blaise Tine	e1c8ff02be	minor update	2024-05-21 12:46:15 -07:00
Blaise Tine	210e4a8e8f	minor update	2024-05-21 12:45:03 -07:00
Blaise Tine	9b79d60507	minor update	2024-05-21 05:39:35 -07:00
Blaise Tine	b3f96e288a	+ support for ZICOND RISC-V extension ... + RTL decode refactoring	2024-05-20 00:17:24 -07:00
Blaise Tine	19beb0728e	minor update	2024-05-12 20:21:23 -07:00
Blaise Tine	60107cf2b6	XRT runtime and simulation support for Vortex AFU (incomplete)	2024-05-11 17:43:49 -07:00