MichaelJSr
883a7aed8d
Changed vector emulation to use VLENB (VLEN / 8) and some merge fixes
2025-02-11 14:43:50 -08:00
MichaelJSr
ac18a5ae82
Merge remote-tracking branch 'upstream/tensor_unit' into simx-vpu
2025-02-11 06:38:59 -08:00
MichaelJSr
b2ad2e5281
Added a vpu and vec units
2025-02-09 17:53:09 -08:00
tinebp
3e7f9cf81c
minor update
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2025-02-07 03:20:24 -08:00
tinebp
6ee2d41a93
minor fix
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2025-02-06 11:52:12 -08:00
tinebp
c93d914e70
minor update
2025-02-06 10:30:07 -08:00
tinebp
631f9c3760
minor update
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2025-02-06 05:13:30 -08:00
tinebp
0ecbcc6f8d
vpu fixes
2025-02-06 04:26:11 -08:00
tinebp
15d2d25350
vpu fixes
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2025-02-05 23:08:03 -08:00
tinebp
b59b30c75b
minor udpate
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2025-02-03 22:40:33 -08:00
tinebp
782d0cd4c4
minor update
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2025-02-03 13:07:34 -08:00
tinebp
f1be2a5808
minor update
2025-02-03 12:51:25 -08:00
tinebp
fbe8538573
TPU updates
2025-02-03 12:46:09 -08:00
tinebp
a920025582
code refactoring to cleanup existing TPU and VPU code in SimX
2025-02-02 23:44:31 -08:00
tinebp
4785736e4d
minor update
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2025-01-26 22:55:22 -08:00
tinebp
38861d9aaf
minor updates
2025-01-26 22:40:34 -08:00
tinebp
82b0eeded6
minor update
2025-01-26 19:35:56 -08:00
tinebp
22398c991d
ramulator memory addressing bug fix + platform memory refactoring
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2025-01-26 06:28:51 -08:00
tinebp
e80ee2c819
minor update
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2025-01-22 04:56:49 -08:00
tinebp
9dc1d3f688
Merge branch 'bug_fixes'
2025-01-22 02:49:55 -08:00
MichaelJSr
6d27575db3
Revert some of "Added ifndef statements for the vector extension anywhere they didn't exist already"
2025-01-14 21:56:39 -08:00
MichaelJSr
a2cfeffcfe
Added ifndef statements for the vector extension anywhere they didn't exist already
...
Added ifndef statements for the vector extension anywhere they didn't exist already
more ifdef statements
more ifdef
Update decode.cpp
Update decode.cpp
Update decode.cpp
2025-01-14 21:29:47 -08:00
tinebp
43b143bba6
bug fixes
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2025-01-14 03:44:53 -08:00
tinebp
87297e0eca
bug fixes
2025-01-14 02:21:17 -08:00
MichaelJSr
929ef1b6e2
Remove unused EXTV code, clean up code, pragma once around vpu.h
2025-01-13 16:45:13 -08:00
tinebp
53900bee4f
bug fixes
2024-12-26 10:01:36 -08:00
tinebp
704f525fd6
memory mem_coalescer miss perf counter
...
RTL perf counters refactoring
2024-12-26 08:00:36 -08:00
tinebp
01974e124f
Merge pull request #216 from sij814/simx2
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Simx ICache DCache Changes
2024-12-18 03:17:14 -08:00
tinebp
a98d2e24e5
rtlsim multibanks
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2024-12-16 22:10:57 -08:00
sij814
cad129c64c
added icache dcache overlap
2024-12-15 14:55:21 -08:00
tinebp
461f2cbbc9
Intel Opae AFU support for multiport
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2024-12-13 21:20:38 -08:00
tinebp
70ade222b1
multiport
2024-12-10 23:25:05 -08:00
tinebp
aa6a47eb11
minor update
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2024-12-05 23:35:15 -08:00
tinebp
115ff2b599
minor fixes
2024-12-05 22:38:04 -08:00
tinebp
6bbcd4ebaf
vector updates with clang formatting
2024-12-05 15:55:57 -08:00
tinebp
6b23d290c3
vector ISA updates
2024-12-05 14:43:51 -08:00
tinebp
5891a1e592
Merge branch 'master' into riscv-vector-isa-simx-clean
2024-12-05 10:17:05 -08:00
tinebp
a760d909cb
minor update
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2024-12-04 21:36:31 -08:00
tinebp
86f20b27dd
SimX multi-ports memory fixes
2024-12-04 21:11:51 -08:00
tinebp
3ace9bbeda
minor updates
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2024-12-04 06:00:19 -08:00
tinebp
30b0daf050
SimX multiports support fixes
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2024-12-03 05:46:33 -08:00
tinebp
24ca4f03aa
minor update
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2024-12-02 19:53:28 -08:00
tinebp
3b454efd56
fixes to SimX's multiports memory support
2024-12-02 17:51:42 -08:00
MichaelJSr
6c2cbdfec2
made -v a valid option for simx simulator
2024-11-28 02:12:01 -08:00
MichaelJSr
5eecd0e987
Added case for vector-test due to different exitcode
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The vector tests need the cluster exitcodes
2024-11-27 23:50:57 -08:00
MichaelJSr
073e0ddd10
Adds the riscv vector extension into simx
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Added vector regression test to ci.yml
2024-11-27 23:22:22 -08:00
tinebp
5844de8c4d
Merge branch 'rtl_cache'
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2024-11-13 22:27:11 -08:00
Blaise Tine
98b58606e5
merge fixes
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2024-10-24 02:18:00 -07:00
Blaise Tine
a7ba377581
minor update
2024-10-16 18:04:11 -07:00
MichaelJSr
0d04423074
Readded the ecall and ebreak instruction traps so that the riscv-vector tests run properly
2024-10-14 10:12:33 -07:00
