201 commits

Author	SHA1	Message	Date
Blaise Tine	13a5370254	register file refactoring	2020-12-05 01:40:50 -08:00
Blaise Tine	478d971389	minor update	2020-12-03 16:21:20 -08:00
Blaise Tine	c3ec4c9e90	minor update	2020-12-03 09:30:59 -08:00
Blaise Tine	f3b1069ce8	adding stream arbiter	2020-12-03 06:40:23 -08:00
Blaise Tine	f575f16f57	minor update	2020-12-01 12:57:02 -08:00
Blaise Tine	b677f724aa	Use skid buffer on CSR IO bus to stop backpressure delay propagation into csr_unit	2020-12-01 12:37:15 -08:00
Blaise Tine	97739e9dcf	RAM blocks inference fixes	2020-11-30 14:02:47 -08:00
Blaise Tine	5758ef9ebf	generic_register reset network optimization	2020-11-29 18:41:36 -08:00
Blaise Tine	ac1883a13f	tabs cleanup	2020-11-28 17:08:01 -05:00
Blaise Tine	eb307edd9c	minor update	2020-11-23 17:34:06 -08:00
Blaise Tine	1795980a52	L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization	2020-11-21 09:47:56 -08:00
Blaise Tine	a1fcdd467a	reset networks optimization	2020-11-16 01:12:02 -08:00
Blaise Tine	fceb561cbd	synchronous reset network optimization: only reset register when required	2020-11-11 20:54:54 -08:00
Blaise Tine	725322807e	fixed DRAM response backpressure inside Cache	2020-11-10 05:24:57 -08:00
Blaise Tine	b14007f930	pipeline optimization: fixed GPR fanout delay to execute units	2020-11-07 02:01:21 -08:00
Blaise Tine	af2bb3b789	cache fixes and opyimization - fmax moved from 162 mhz to 220 mhz!!!	2020-11-05 03:49:50 -08:00
Blaise Tine	4c6a74fa87	cache refactoring - phase 3 - added dedicated pipeline stage for tag access	2020-11-04 03:21:30 -08:00
Blaise Tine	ba81d76e02	cache refactoring - phase 2	2020-11-03 04:51:40 -08:00
Blaise Tine	5be1d85648	cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count	2020-11-02 01:50:12 -08:00
Blaise Tine	43ae82e788	vlsim fix, verilator fst trace, use ram optimization	2020-10-25 16:40:50 -07:00
Blaise Tine	e6466b887c	minor update	2020-10-20 08:45:21 -07:00
Blaise Tine	7529f72c5d	fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags	2020-10-20 05:32:55 -07:00
Blaise Tine	32da50816f	scope refactoring: adding modules definitions to VCD trace	2020-10-12 23:26:02 -04:00
Blaise Tine	309dd48fc6	scope bug fixes	2020-10-06 03:59:27 -04:00
Blaise Tine	4e1007e5b2	scope refactoring	2020-10-03 18:53:21 -04:00
Blaise Tine	42e3b6c45d	fixed lmp_mult parameters, ram init filepath	2020-09-04 07:51:46 -07:00
Blaise Tine	af84e01856	minor update	2020-08-31 06:17:49 -07:00
Blaise Tine	0a0b28aac0	minor update - 206-214 mhz	2020-08-29 05:14:08 -07:00
Blaise Tine	efbe4a07ef	serial divider optimization	2020-08-25 03:23:57 -07:00
Blaise Tine	ee81e81818	adding using serial divider to save area cost	2020-08-25 02:29:27 -07:00
Blaise Tine	f292e5003d	quartus build fixes	2020-08-23 22:04:46 -07:00
Blaise Tine	1c9445745f	fp_noncomp fixes	2020-08-23 16:53:28 -07:00
Blaise Tine	96f5432592	minor update	2020-08-22 13:56:07 -07:00
Blaise Tine	0b355f228e	ibuffer addition	2020-08-22 00:22:04 -07:00
Blaise Tine	6c12391338	pipeline refactoring - fmax >= 222 mhz	2020-08-14 21:50:14 -07:00
Blaise Tine	65415d2bbc	getting dogfood tests passing on Verilator!	2020-08-09 18:13:12 -04:00
Blaise Tine	cd29362d10	fixed FPU handshake, optimized writeback's critical path	2020-08-07 10:11:54 -07:00
Blaise Tine	ffd9515881	added altera fpu modules	2020-08-05 15:53:59 -07:00
Blaise Tine	d8bdaa2b4e	minor update	2020-08-01 14:38:31 -07:00
Blaise Tine	31ee824862	merged fpu_port branch	2020-07-31 17:13:22 -04:00
Blaise Tine	4bdab8903e	merge	2020-07-31 16:49:59 -04:00
Blaise Tine	27e95530ef	pipeline optimization	2020-07-30 03:06:01 -07:00
Blaise Tine	c2dd0a8b39	modelsim fixes && pipeline optimization	2020-07-28 14:20:23 -07:00
Blaise Tine	f3721c523f	minor update	2020-07-28 06:02:32 -04:00
Blaise Tine	7c86b68977	pipeline refactoring: centralized issue buffer	2020-07-26 11:21:08 -04:00
Blaise Tine	dc7efbcfb4	pipeline refactoring	2020-07-21 05:22:47 -04:00
Blaise Tine	25f66e6490	pipeline refactoring	2020-07-19 05:03:47 -04:00
trmontgomery	ed3a0cfa4d	added rsp map	2020-07-19 00:08:09 -04:00
Blaise Tine	bdfacf709c	yosys synthesis refactoring	2020-07-10 18:56:41 -04:00
Blaise Tine	5d088d67c8	Gather FPGA perf stats	2020-07-01 09:30:12 -07:00