Commit graph

201 commits

Author SHA1 Message Date
Blaise Tine
75d66dc335 fix sources.txt, run_ase.sh 2020-06-29 12:52:28 -07:00
Blaise Tine
a70562d386 set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18 2020-06-29 08:03:19 -07:00
felsabbagh3
e919e452b9 Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2020-06-28 20:01:49 -07:00
felsabbagh3
21566cdcd7 Fixed Single Core with Optimizations 2020-06-28 19:38:36 -07:00
Blaise Tine
eb67788bf2 Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2020-06-28 14:45:01 -07:00
Blaise Tine
27ea36440e multiplier fixes 2020-06-28 14:39:18 -07:00
felsabbagh3
ffb760cf73 Optimized cache writeback path by 1) VX_fair_arbiter and 2) Added a wb register between LSU and WB arbiter 2020-06-28 14:27:47 -07:00
Blaise Tine
baf7d3bb92 minor update 2020-06-27 17:46:45 -04:00
Blaise Tine
8302641510 fpga fixes 2020-06-27 14:03:20 -07:00
Blaise Tine
e6cc221a44 refactoring 2020-06-23 10:59:30 -07:00
Blaise Tine
0a01385a2c few updates 2020-06-23 09:28:24 -07:00
Blaise Tine
d3440de403 round robin arbiter + auto buffered queue + fixed dcache arbiter 2020-06-20 17:56:04 -04:00
Blaise Tine
68d9fc9a75 driver basic test and demo test refactoring 2020-06-19 09:12:07 -07:00
Blaise Tine
9850a1f890 minor fixes 2020-06-15 00:20:56 -07:00
Blaise Tine
75af29febb scope refactoring 2020-06-13 11:47:28 -07:00
Blaise Tine
d6b0ef2b3c scope refactoring + snoop invalidate 2020-06-12 00:04:31 -07:00
Blaise Tine
19f263c772 scope fixes 2020-06-09 20:49:36 -07:00
Blaise Tine
457783322b scope fixes 2020-06-09 07:03:52 -07:00
Blaise Tine
9575fe9a51 scope fixes 2020-06-08 06:54:47 -07:00
Blaise Tine
170c88f295 scope fixes 2020-06-08 04:25:28 -07:00
Blaise Tine
9ae38433fb VX_pipeline refactoring + logic analyzer 2020-06-06 01:52:44 -04:00
Blaise Tine
9eb0389717 minor update 2020-06-03 06:40:25 -04:00
Blaise Tine
04fc34b848 minor update 2020-06-03 03:05:45 -07:00
Blaise Tine
e01c411b20 opae rtl fixes 2020-06-01 23:06:13 -07:00
Blaise Tine
9e5885b820 adding dram writeenable support + scheduler bug fixes 2020-05-27 19:00:23 -04:00
Blaise Tine
cf22ef2bf3 minor update 2020-05-21 13:42:08 -04:00
Blaise Tine
d12c40131e optimize generic_queue to support simple model for smaller size queues 2020-05-21 04:04:27 -04:00
Blaise Tine
276fa5c919 optimize generic_queue to support simple model for smaller size queues 2020-05-21 03:34:03 -04:00
Blaise Tine
b5569dd525 OPAE rtl fixes 2020-05-20 12:08:10 -07:00
Blaise Tine
d6c87dbb0a added debug print states or rtl 2020-05-16 14:19:17 -04:00
Blaise Tine
d623ef4029 snooping response handling fix 2020-05-14 23:05:46 -04:00
Blaise Tine
13dfd5c8c7 rtl multicore fix 2020-05-07 02:20:12 -04:00
Blaise Tine
de9fc68ccc opae fixes 2020-05-06 21:14:53 -07:00
Blaise Tine
b7e892ee16 rtl refactoring 2020-05-05 10:46:48 -04:00
Blaise Tine
f142afac80 rtl refactoring 2020-05-04 20:12:05 -04:00
Blaise Tine
a1dc90b951 rtl cache refactory 2020-04-30 17:12:18 -04:00
Blaise Tine
3cf1a5074b RTL code refactoring 2020-04-23 12:50:02 -04:00
Blaise Tine
77a52ea20b optimized opae cci to dev memcpy using double buffering and request window to work around unordered read requests 2020-04-23 01:30:45 -07:00
Blaise Tine
f53256f854 quartus projects 2020-04-21 12:28:37 -07:00
Blaise Tine
cb0afd3eec fix quartus build 2020-04-21 00:55:18 -07:00
Blaise Tine
d85c0af5d6 remove tab spaces 2020-04-21 03:19:47 -04:00
Blaise Tine
43a8bf4326 RTL code refactoring 2020-04-21 01:52:12 -04:00
Blaise Tine
20ae78f434 fix simX build 2020-04-21 01:31:32 -04:00
Blaise Tine
cfa8626bf7 RTL code refactoring 2020-04-20 23:44:30 -04:00
Blaise Tine
d79e36912f fix opae build 2020-04-20 12:51:42 -07:00
Blaise Tine
3cbecfcef0 opae build fix 2020-04-20 12:32:01 -07:00
Blaise Tine
b76f8696bd removing *.vh file for opae build 2020-04-20 15:07:27 -04:00
Blaise Tine
8e7046a388 RTL code refactoring 2020-04-20 14:05:08 -04:00
Blaise Tine
1a2823da0d RTL code refactoring 2020-04-20 13:52:24 -04:00
Blaise Tine
a0e15af0dc RTL code refactoring 2020-04-20 13:01:42 -04:00