43 commits

Author	SHA1	Message	Date
Blaise Tine	d7737542e4	cache uuid support	2021-12-09 20:43:22 -05:00
Blaise Tine	41d7e6c63a	cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes	2021-11-30 07:08:15 -05:00
Blaise Tine	fe862f64b1	dispatch refactoring	2021-10-19 15:16:00 -04:00
Blaise Tine	1cd833d2c4	minor fixes	2021-10-11 19:02:13 -07:00
Blaise Tine	29aba92bf1	minor update	2021-09-30 06:14:05 -07:00
Blaise Tine	a801a16062	instruction decode refactoring fixing naming collision	2021-08-29 20:07:34 -07:00
Blaise Tine	4336dcb2a8	minor scope analyzer fix	2021-08-13 19:23:57 -07:00
Blaise Tine	cc259f60f6	minor update	2021-08-11 15:39:21 -07:00
Blaise Tine	4e4aa33a50	minor update	2021-08-08 03:09:28 -07:00
Blaise Tine	0debdd3fe7	minor update	2021-08-08 02:59:30 -07:00
Blaise Tine	b1eef0fb7c	warp scheduler optimization	2021-08-07 23:45:01 -07:00
Blaise Tine	3b7da61245	minor update	2021-07-31 03:30:35 -07:00
Blaise Tine	4ffbcb336f	minor update	2021-07-22 14:20:02 -07:00
Blaise Tine	7e0dc81cee	minor update	2021-06-23 04:19:13 -07:00
Blaise Tine	41069ba188	non-cacheable memory address fixes	2021-06-06 20:54:36 -07:00
Blaise Tine	3071fb7a29	adding support for non-cacheable memory addressing	2021-06-06 13:35:55 -07:00
Blaise Tine	762c5da237	minor update	2021-05-27 15:23:58 -07:00
Blaise Tine	8f451aa74c	minor update	2021-05-04 08:01:49 -07:00
Blaise Tine	8410c49f53	code refactoring: DRAM => MEM renaming	2021-04-26 00:58:48 -07:00
Blaise Tine	b023496ecb	minor update	2021-03-01 03:00:58 -08:00
Blaise Tine	7560202f8b	cache bank refactoring - removing unecessary core response fifo & restoring single port data access	2021-02-21 21:47:46 -08:00
Blaise Tine	a046bd7a73	cache pipeline optimization	2021-01-17 17:19:52 -08:00
Blaise Tine	d4e7b28be8	cache refactoring	2021-01-17 00:18:56 -08:00
Blaise Tine	5b80484123	minor updates	2021-01-16 14:16:10 -08:00
Blaise Tine	fe64c47f60	ccip write fix	2021-01-14 22:49:06 -08:00
Blaise Tine	464c4f4bd8	minor updates	2021-01-12 20:16:59 -08:00
Blaise Tine	4d55118545	cache pipeline optimization - moved tag access to stage0	2021-01-03 23:10:41 -05:00
Blaise Tine	abe32ed553	cache optimization - moved read requests to stage1 and eliminating stage3	2020-12-31 07:40:58 -08:00
Blaise Tine	9f128085d5	scoreboard optimization - using writeback's end-of-packet status	2020-12-30 06:47:56 -08:00
Blaise Tine	3fdc49971c	minor update	2020-12-24 09:22:44 -08:00
Blaise Tine	4bbd7bf408	performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,	2020-12-19 02:45:06 -08:00
Blaise Tine	13a5370254	register file refactoring	2020-12-05 01:40:50 -08:00
Blaise Tine	def6a35693	shared memory optimization	2020-11-29 15:04:31 -08:00
Blaise Tine	b85391389b	rename MSRQ to MSHR	2020-11-28 17:32:00 -05:00
Blaise Tine	af2bb3b789	cache fixes and opyimization - fmax moved from 162 mhz to 220 mhz!!!	2020-11-05 03:49:50 -08:00
Blaise Tine	4c6a74fa87	cache refactoring - phase 3 - added dedicated pipeline stage for tag access	2020-11-04 03:21:30 -08:00
Blaise Tine	3fe31fc337	fixed afu to cpu mempcy hang	2020-10-28 14:19:13 -07:00
Blaise Tine	9a9f7955f0	basic test timing + scope tracing ccip	2020-10-27 17:04:04 -04:00
Blaise Tine	58b8e82908	scope fixes ...	2020-10-13 17:09:22 -04:00
Blaise Tine	4bfc4ee78f	scope fixes	2020-10-13 08:44:55 -07:00
Blaise Tine	32da50816f	scope refactoring: adding modules definitions to VCD trace	2020-10-12 23:26:02 -04:00
Blaise Tine	309dd48fc6	scope bug fixes	2020-10-06 03:59:27 -04:00
Blaise Tine	4e1007e5b2	scope refactoring	2020-10-03 18:53:21 -04:00