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83 commits

Author SHA1 Message Date
Eric Matthews
583976c7ea Share nexys config between simulation and hardware wrapper 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2023-04-29 18:48:16 -04:00
Eric Matthews
17c45f0050 Consolidate BRAM implementations 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2023-04-17 13:15:24 -04:00
Eric Matthews
6b80905045 Reorganize source files 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2023-04-14 20:21:05 -04:00
Eric Matthews
9a188e39f9 Remove unused rtl files 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2023-04-11 19:45:27 -04:00
Eric Matthews
ac362d0b5b Move instruction decode to units 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2023-01-26 16:34:38 -05:00
Eric Matthews
47358a901c Add custom unit template 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2023-01-24 19:06:45 -05:00
Eric Matthews
1e9343a91c Restructure registerfile muxes 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2023-01-20 19:30:04 -05:00
Eric Matthews
b5f792048b Add nexys 7 example 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-11-14 13:59:24 -05:00
Eric Matthews
4d42d3445d Simulation tracing improvements 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-11-14 12:03:35 -05:00
Eric Matthews
95bc8d244c Reduce data cache latency 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-07-05 15:38:36 -04:00
Eric Matthews
fe3c0384fc Rework instruction cache addressing logic 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-07-05 15:08:38 -04:00
Eric Matthews
6aeac17b9d Rework simulation stats 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-27 16:28:17 -04:00
Eric Matthews
bae3594995 load-store-queue code cleanup 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-12 22:21:52 -04:00
Eric Matthews
90c9dd6343 unified fetch and load-store sub_unit interfaces 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-03-25 13:27:07 -04:00
Eric Matthews
9cff8c5afb renamed occurrences of taiga to cva5 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-03-05 12:53:49 -08:00
Eric Matthews
dec39b9041 removed old lut_ram 2022-01-18 11:29:35 -08:00
Eric Matthews
e1dbb108d5 switched toggle-mem to new lutram blocks 2022-01-18 11:29:35 -08:00
Eric Matthews
2292cbcad5 init/clear counters changed to un-ordered 2022-01-18 11:29:35 -08:00
Eric Matthews
d3c5471907 prep for CSR split 2022-01-18 11:29:35 -08:00
Eric Matthews
4c3d7f025e CSR/GC restructuring 2022-01-18 11:29:35 -08:00
Eric Matthews
d87f03bf29 verilator cleanups 2022-01-18 11:29:35 -08:00
Eric Matthews
a4ac269e4c new priority encoder 2022-01-18 11:29:35 -08:00
Eric Matthews
40f5e808fb Div improvements 2022-01-18 11:29:35 -08:00
Eric Matthews
e875eecba2 renaming rework 2022-01-18 11:29:35 -08:00
Eric Matthews
dfec0e0d46 restructured toggle memories 2022-01-18 11:29:35 -08:00
Eric Matthews
78155870c1 seperated load and store queues 2022-01-18 11:29:35 -08:00
Zavier Aguila
01700d108e Updated taiga.mak. Removed untested simulated DDR features. 2022-01-18 11:29:35 -08:00
Eric Matthews
e8cd051c40 makefile fix 2020-07-29 16:13:38 -07:00
Eric Matthews
a15921cdf3 makefile refactor 2020-07-29 10:29:14 -07:00
Eric Matthews
11150703f8 new assertion controls 2020-06-29 20:46:29 -07:00
Eric Matthews
27caeb5514 div algorithms pruned and div unit input buffering reduced 2020-06-07 18:31:11 -07:00
Eric Matthews
f0e8aaff14 merged instruction metadata and ID management 2020-06-07 14:48:08 -07:00
Eric Matthews
1cf2513700 support for multiple write ports on regfile 2020-06-03 13:50:20 -07:00
Eric Matthews
a0f4368f85 execution and writeback changes for new ID system 2020-06-03 13:50:20 -07:00
Eric Matthews
06f3c14115 initial ID rework for processor front end 2020-06-03 13:49:50 -07:00
Eric Matthews
b202582d08 moved pre_decode logic into decode_and_issue in prep for decode and issue split 2020-06-03 13:46:41 -07:00
Zavier Aguila
fae4b40d89 DDR simulation 2020-06-03 20:39:35 +00:00
Eric Matthews
59554ff15e basic illegal instruction support 2020-05-07 16:41:35 -07:00
Eric Matthews
3c37ec0ae0 code cleanup: converted set/clr register usage into a module 2020-04-02 15:32:02 -07:00
Eric Matthews
8ea982f1ab lsq updates 2020-03-10 11:37:22 -07:00
Eric Matthews
bb534d617f Added L2 arbiter to verilator test platform 2020-03-05 15:00:36 -08:00
Eric Matthews
20bde562ef initial store buffer design 2020-02-16 14:19:17 -08:00
Eric Matthews
79f269dc57 code cleanups 2020-01-22 19:59:33 -08:00
Eric Matthews
870530437b gitignore for logs 2020-01-22 15:25:58 -08:00
Zavier
06d82770c8 Added Trace Flag to Makefile 2019-12-17 17:07:34 -08:00
Eric Matthews
928282ade9 barrel shifter changes, Store forwarding changed to be internal to L/S unit, various minor cleanups 2019-12-13 12:54:32 -08:00
Eric Matthews
3abc83c503 Improved makefile dependency generation 2019-12-08 15:26:07 -08:00
Eric Matthews
6b174f370f decode rename 2019-12-08 14:24:10 -08:00
Eric Matthews
0558c63557 div interface refactor 2019-11-19 18:06:20 -08:00
Eric Matthews
4405f17510 updated compile order with missing div algorithms 2019-11-15 14:44:35 -08:00