Jalali
107d29d619
ISA spec : Update ISA specification ( #1044 )
2023-02-06 10:30:12 +01:00
Hassan Raza
b817386ff4
add cva6_testharness documentation ( #992 )
2022-12-08 09:35:32 +01:00
Jalali
3a8cc95eaa
ISA spec : fix some instructions format ( #999 )
2022-11-24 10:27:20 +01:00
Mike Thompson
bf5a74cae5
[skip ci] Add hierarchy to the CVA6 documentation ( #995 )
...
* Clarify scope of Verilator model
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* Update repo user docs
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* Update repo user docs
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* CORE-V not COREV
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* First release is v0.1.0
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* Fix typo
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* Create documentation hierarchy
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
2022-11-16 11:19:37 -05:00
Mike Thompson
23217ad8bd
First release identifier is v0.1.0 ( #994 )
2022-11-10 14:29:09 +01:00
Jalali
6d74e04575
ISA Specification for cva6 ( #985 )
2022-11-09 14:58:58 +01:00
AEzzejjari
93cd372c74
Add AXI chapter ( #984 )
2022-11-09 14:54:59 +01:00
Jérôme Quévremont
f346d6604f
Scratchpad can also be separate from caches ( #981 )
...
To ease the implementation. As we'll target FPGA and ASIC (not ASSP), we do not need a "one size fits all" solution.
2022-10-22 08:22:21 +02:00
Tamas Olaszi
cfb81565b7
Add CV32A6 CSR specification in .rst and IP-XACT format ( #952 )
2022-10-06 12:53:36 +02:00
JeanRochCoulon
3da41f7908
Revisit system/subsystem/module/submodule terminology ( #953 )
2022-09-12 11:07:12 +02:00
JeanRochCoulon
e60330ce90
Design Spec initial commit: description of introduction, system and frontend ( #949 )
2022-09-05 23:40:15 +02:00
Mike Thompson
767c465cfb
Introduce CV32A60X as first release ( #916 )
2022-06-28 14:04:06 +02:00
jquevremont
c318548f22
CVA6 specification (reStructuredText format) ( #855 )
...
* Create cva6_requirement_specification.rst
Restarting from scratch after Eclipse check fail.
Taken into account DBees review in PR #851 .
Removed no-reset FPGA design style (risky, very limited gain in nowadays FPGAs).
* Add folder
Add folder
* Delete images
* Create ignore.txt
Workaround to create folder
* Add files via upload
CVA6 scope picture
* Delete ignore.txt
Remove file
2022-04-28 08:13:29 -07:00
RanjanThales
0065b28def
doc: Add cva6_ug_csr.adoc ( #817 )
...
* added user_guide/CVA6_UG_CSR.adoc
* added docs/user_guide/CVA6_UG_CSR.adoc
* Update docs/user_guide/CVA6_UG_CSR.adoc
Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
* Update cva6_ug_csr.adoc
Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
2022-02-07 15:01:52 +01:00
Nils Wistoff
163eb93947
docs: add documentation for SoC
...
* Memory Map
* PLIC interrupt sources
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
2020-12-01 15:04:15 +01:00
Florian Zaruba
f8481cb54e
doc: Move to read the docs
2020-07-26 13:38:15 +02:00
Daichou
1b65b8865a
docs: fix document build misleading instructions
2020-07-14 16:33:33 +02:00
Moritz Schneider
a3051e8636
Add PMP documentation
2020-07-14 16:08:38 +02:00
Florian Zaruba
1ebca456ad
ariane: Replace branchpredict_t with bp_resolve_t
...
The new name better captures the meaning of the signal.
2019-06-04 10:36:17 +02:00
Florian Zaruba
932ef8a351
⬆️ Update jekyll dependency
2018-11-26 17:54:04 +01:00
Florian Zaruba
4558960b88
Small pre-release clean-up
2018-11-23 11:37:14 +01:00
Florian Zaruba
46399072da
Update block diagram
2018-05-06 16:43:53 +02:00
Florian Zaruba
90aec89a2f
Remove old and merged documentation
2018-01-25 10:58:04 +01:00
Florian Zaruba
42d577e519
Update documentation
2018-01-25 10:47:46 +01:00
Florian Zaruba
d8261ad8dd
Add new documentation framework
2018-01-24 13:04:33 +01:00
Florian Zaruba
0aa769677b
Remove TB directory
2017-07-26 23:47:49 +02:00
Florian Zaruba
cba2c9769d
📝 Update Ariane block diagram
2017-06-28 23:31:27 +02:00
Florian Zaruba
7bb46a8556
[WIP] Implement return from exception
2017-06-01 16:55:15 +02:00
Florian Zaruba
be9d35da29
📝 Slightly update LSU timing diagrams
2017-05-29 16:41:08 +02:00
Florian Zaruba
2d7d0a880e
📝 Updated LSU <-> D$ information
2017-05-29 11:09:59 +02:00
Florian Zaruba
b8284ddb80
📝 Add D$ interface documentation
2017-05-29 10:41:57 +02:00
Florian Zaruba
ba04445d27
🎨 Remove pre-fetch buffer, module was redundant
2017-05-27 19:12:13 +02:00
Florian Zaruba
35bdeb69d0
📝 Add further documentation and clean-up
2017-05-27 18:48:50 +02:00
Florian Zaruba
fbfb0f4f24
📝 Update main block diagram
2017-05-16 19:17:58 +02:00
Florian Zaruba
ad571c8ad4
📝 Add updated pipeline diagram
2017-05-08 19:18:56 +02:00
Florian Zaruba
a813180137
📝 Add pipeline diagram to diagram section
2017-05-07 23:15:10 +02:00
Florian Zaruba
ab08a4e228
📝 Add further clarification on timings
2017-05-07 15:05:01 +02:00
Florian Zaruba
a752a78cfd
📝 Add timing diagram for memory interface
2017-05-07 13:09:05 +02:00
Florian Zaruba
5fe1d7f067
📝 Add the ability to display timing diagrams
2017-05-07 12:37:18 +02:00
Florian Zaruba
4b75332d10
📝 Update documentation with CSR FU
2017-05-05 11:28:55 +02:00
Florian Zaruba
6c4a9c2452
📝 Add some information about exception handling
2017-05-04 19:56:52 +02:00
Florian Zaruba
b5e62fd91b
🐛 Fix missing pin, wrong fetch data width
2017-05-03 18:29:36 +02:00
Florian Zaruba
c65f9a9efa
📝 Add basic information on the testbenches
2017-04-28 12:32:26 +02:00
Florian Zaruba
fddec3272d
LSU control implement, completely untested
2017-04-26 16:53:04 +02:00
Florian Zaruba
69a6da981b
Implemented store queue for speculative st
2017-04-25 18:18:58 +02:00
Florian Zaruba
367ebf6cca
Add PTW stub, clear interface definition missing
2017-04-24 11:18:16 +02:00
Florian Zaruba
5810113c5b
📝 Apply memory restructuring changes to BD
2017-04-21 14:09:13 +02:00
Florian Zaruba
62c20b47cf
📝 Updated images to reflect latest changes
2017-04-21 11:03:35 +02:00
Florian Zaruba
fd4234a5f0
📝 Added image sources to figure folder
2017-04-21 10:53:07 +02:00
Florian Zaruba
b17fafee55
Updated README with BTB information
2017-04-19 20:59:24 +02:00
