Côme
4df49a6b0f
superscalar: make SuperscalarEn a CVA6Cfg attribute ( #2322 )
2024-07-05 14:09:48 +02:00
Florian Zaruba
377b0de154
Fix SuperScalar config and add CVA6Cfg to first pass decoder ( #2047 )
...
* Add `CVA6Cfg` to first pass decoder
* Fix `verilator` `SELRANGE` warnings
* Update core/decoder.sv
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
* Update core/cva6_accel_first_pass_decoder_stub.sv
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
* Update core/decoder.sv
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
* Update core/frontend/instr_queue.sv
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
---------
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
2024-04-17 16:34:08 +02:00
JeanRochCoulon
5df5a5c247
Define InstrTlbEntries, DataTlbEntries, cfg.NrLoadPipeRegs, NrStorePipeRegs, DcacheIdWidth as CVA6 parameters ( #2034 )
2024-04-12 09:06:35 +02:00
Côme
1c529d68ce
superscalar: return 2 instructions from instruction queue ( #2022 )
2024-04-09 16:39:24 +02:00
Côme
ec44b22920
superscalar: fetch 64 bits ( #2013 )
2024-04-08 11:25:39 +02:00
Florian Zaruba
38e8c059b2
Parameterization and other fixes for downstream project ( #1950 )
...
* Bender fixes and switch to `cva6_fifo_v3`
* cfg: Fix verilator warnings
* Bender: Fix yml
* acc_dispatcher: Add `csr_addr_i`
* parameterization: Fox AXI_USER_EN warning
* wb_cache: Fix Verilator Lint warnings
* cva6_fifo_v3: Add to Flist
* parameterization: Address review concerns
* Switch to `cva6_fifo_v3`
* tracer: Remove tracer interface
The interface made a bunch of problems with the
typedefs so I've removed it.
---------
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
2024-04-05 13:02:18 +02:00
JeanRochCoulon
4423feb06a
Rename ZiCondExtEn and FPGA_EN parameters ( #1992 )
2024-04-02 15:37:58 +02:00
Bruno Sá
86e1408666
Hypervisor extension ( #1938 )
...
Support 64bit H extension
2024-03-21 10:28:01 +01:00
Côme
bd4b57cc64
Parametrization step 3 part 3 (last) ( #1940 )
2024-03-18 16:19:52 +01:00
Côme
4817575de9
Parametrization step 3 part 2 ( #1939 )
2024-03-18 12:06:55 +01:00
Côme
987c645bb7
Parametrization step 3 ( #1935 )
...
This is the third step for #1451 . Many values are moved but not all values are moved yet
* move NR_SB_ENTRIES & TRANS_ID_BITS
* remove default rvfi_instr_t from spike.sv
* fifo_v3: ariane_pkg::FPGA_EN becomes a param
* move FPGA_EN
* inline wt_cache_pkg::L15_SET_ASSOC
* move wt_cache_pkg::L15_WAY_WIDTH
* inline wt_cache_pkg::L1I_SET_ASSOC
* inline wt_cache_pkg::L1D_SET_ASSOC
* move wt_cache_pkg::DCACHE_CL_IDX_WIDTH
* move ICACHE_TAG_WIDTH
* move DCACHE_TAG_WIDTH
* move ICACHE_INDEX_WIDTH
* move ICACHE_SET_ASSOC
* use ICACHE_SET_ASSOC_WIDTH instead of $clog2(ICACHE_SET_ASSOC)
* move DCACHE_NUM_WORDS
* move DCACHE_INDEX_WIDTH
* move DCACHE_OFFSET_WIDTH
* move DCACHE_BYTE_OFFSET
* move DCACHE_DIRTY_WIDTH
* move DCACHE_SET_ASSOC_WIDTH
* move DCACHE_SET_ASSOC
* move CONFIG_L1I_SIZE
* move CONFIG_L1D_SIZE
* move DCACHE_LINE_WIDTH
* move ICACHE_LINE_WIDTH
* move ICACHE_USER_LINE_WIDTH
* move DCACHE_USER_LINE_WIDTH
* DATA_USER_WIDTH = DCACHE_USER_WIDTH
* move DCACHE_USER_WIDTH
* move FETCH_USER_WIDTH
* move FETCH_USER_EN
* move LOG2_INSTR_PER_FETCH
* move INSTR_PER_FETCH
* move FETCH_WIDTH
* transform SSTATUS_SD and SMODE_STATUS_READ_MASK into functions
* move [SM]_{SW,TIMER,EXT}_INTERRUPT into a structure
* move SV
* move vm_mode_t to config_pkg
* move MODE_SV
* move VPN2
* move PPNW
* move ASIDW
* move ModeW
* move XLEN_ALIGN_BYTES
* move DATA_USER_EN
* format: apply verible
2024-03-15 17:21:34 +00:00
Côme
aed4ed7c23
move functions into modules ( #1926 )
2024-03-13 17:46:33 +01:00
JeanRochCoulon
301f18a5f4
Improve FRONTEND description ( #1914 )
2024-03-11 12:52:35 +01:00
Côme
32a3cd56ee
Parametrization step 2 ( #1908 )
2024-03-08 22:53:42 +01:00
JeanRochCoulon
f9e6a22960
[HOTFIX] Fix ras.sv ( #1887 )
2024-03-05 13:32:39 +01:00
JeanRochCoulon
483ef90127
Update frontend module description ( #1882 )
2024-03-04 23:18:27 +01:00
JeanRochCoulon
3f8649ec7e
Table builder for specification ( #1814 )
2024-02-08 10:54:47 +01:00
JeanRochCoulon
9d0c700f42
port_builder generates the table of ports ( #1805 )
2024-02-06 12:06:13 +01:00
Guillaume Chauvon
fa101fae7a
Parameterize TVAL to reduce size in embedded ( #1784 )
2024-01-25 15:47:06 +01:00
AEzzejjari
738d53af1c
Code coverage: condition RTL With parameters ( #1703 )
2023-12-13 07:52:47 +01:00
AEzzejjari
1faaec09bc
Code_coverage: condition RTL with the debug parameter ( #1582 )
2023-10-31 17:35:59 +01:00
André Sintzoff
7cd183b710
verible-verilog-format: apply it on core directory ( #1540 )
...
using verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format
with default configuration
Note: two files are not correctly handled by verible
- core/include/std_cache_pkg.sv
- core/cache_subsystem/cva6_hpdcache_if_adapter.sv
2023-10-18 16:36:00 +02:00
Fatima Saleem
d3343f5210
resolving lint warnings ( #1520 )
2023-10-09 22:38:05 +02:00
Florian Zaruba
93782ddfb5
Merge CVA6Cfg and ArianeCfg ( #1321 )
2023-09-28 11:41:38 +02:00
Florian Zaruba
91df62885f
Parametrize debug module ( #1382 )
2023-09-13 16:22:24 +02:00
JeanRochCoulon
1db42ee8da
Add variant into CVA6 parameter ( #1320 )
...
* Variane as CVA6 parameter
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* fix FPGA build
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Fix tipo in cva6.sv
* fix lint warnings
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Fix is_*_fpr functions
* remove blank lines
* set IsRVFI out of CVA6Cfg
* define config_pkg
* Fix ariane_pkg comments
* Fix Lint from André's feedbacks
* Fix parameter transmission
* Fix replace CVA6Cfg by CVA6ExtendCfg in cva6.sv
* fix add CVA6Cfg in instr_queue, instr_scan and pmp parameters
---------
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: ALLART Come <come.allart@thalesgroup.com>
2023-08-22 14:04:06 +02:00
Côme
18766f186e
fix prediction shift for BHT and BTB ( #1337 )
...
* add labels to if/else blocks for branch prediction
* add labels to if/else blocks for caches
* fix prediction shift for BHT and BTB
2023-08-18 10:26:26 +02:00
Enrico Zelioli
49d1262512
[FIX] m/sret optimization ( #1333 )
...
Remove m/sret stall penalty by removing the icache miss
Co-authored-by: Enrico Zelioli <ezelioli@student.ethz.ch>
2023-08-14 14:24:01 +02:00
Florian Zaruba
dc103cd49f
Clean-up README.md and top-level directory ( #1318 )
...
* Clean-up README.md and top-level directory
This removes the duplicate `scripts` and `util` directories. Furthermore
the README is condensed by collapsing the citation and adding the
CITATION file to the repository.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
* Re-name icache req/rsp structs
The structs used to communicate with the icache have contained the
direction, which makes no sense for structs since they inherently don't
have any direction.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
---------
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
2023-07-28 08:32:48 +02:00
Domenic Wüthrich
1a13d6c678
Add New Stall and Flush Signals to acc_dispatcher ( #1317 )
...
* [lsu] Add external store buffer pending stall signal
* [controller] Add external acc request pipeline flush signal
* [frontend] Do not increment commit pc on flush if commit stage is halted
* [acc_dispatcher] Add new store buffer stall and flush pipeline ctrl signals
* [acc_dispatcher] Add top module passable config type and parameter
* [cva6] Pass on missing CVA6Cfg parameter to acc_dispatcher
2023-07-26 13:50:38 +02:00
JeanRochCoulon
279ce9fb9b
Define RVFI as cva6 parameter ( #1293 )
2023-07-19 08:21:39 +02:00
JeanRochCoulon
5284f828e4
declare cva6_cfg_t to pass the configuration through the hierarchy ( #1287 )
...
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-07-01 17:24:21 +02:00
JeanRochCoulon
5157e2de9d
Move ariane_cfg_t definition from ariane_pkg to in cva6_config_pkg ( #1056 )
2023-02-13 23:49:27 +01:00
sébastien jacq
3b55657552
BHT optimized for fpga ( #1039 )
...
It counts and saves the saturation bits in D flip-flops for
the ASIC version and in a three-port asynchronous read memory
for the FPGA version.
FPGA flushing is not supported because the frontend module
flushing signal is not connected.
2023-02-01 16:37:44 +01:00
sébastien jacq
6deffb27d7
BTB optimization for FPGA targets ( #1016 )
2022-12-15 13:24:45 +01:00
JeanRochCoulon
28c620a93a
fix dm package dependency ( #1011 )
2022-12-09 17:51:30 +01:00
JeanRochCoulon
52fdcc9429
Fix the AXI_USER_WIDTH value and add some begin/end in frontend.sv ( #961 )
2022-09-22 17:33:15 +02:00
JeanRochCoulon
a9c7b4f1e1
Cvvdev/dev/formating4 ( #920 )
...
Several format cleanings:
- split load_store_unit.sv to create lsu_bypass.sv
- add several "begin" and "end"
2022-06-28 22:15:55 +02:00
sébastien jacq
c26bda3f7b
Make C extension optional ( #833 )
...
Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com>
2022-03-25 16:01:17 +01:00
Gianmarco Ottavi
010eed815b
Fix branch prediction for compressed instruction with unaligned addresses ( #756 )
...
Signed-off-by: Gianmarco Ottavi <gianmarco@openhwgroup.org>
Co-authored-by: Gianmarco Ottavi <gianmarco@openhwgroup.org>
2021-10-10 11:09:45 +02:00
Gianmarco Ottavi
924ec9c2e0
Fix performance bug on calls via BTB ( #753 )
...
Signed-off-by: Gianmarco Ottavi <gianmarco@openhwgroup.org>
Co-authored-by: Gianmarco Ottavi <gianmarco@openhwgroup.org>
2021-10-09 10:20:39 +02:00
André Sintzoff
3ddf797e95
Re-organize CVA6 and APU ( #725 )
...
* Initial repository re-organization (#662 )
Initial attempt to split core from APU.
Signed-off-by: MikeOpenHWGroup <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@invia.fr>
Compile `corev_apu` (#667 )
* Makefile verilates corev_apu
* Cleanup README
* Fix URL to repo
* Cleaned-up Makefile verilates corev_apu
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
Add extended verification support (#685 )
* Makefile, riscv_pkg.sv: Select C64A6 or CV32A6
according to variant variable
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* add RVFI tracer and debug support
New files: rvfi_pkg.sv, rvfi_tracer.sv, ariane_rvfi.pkg.sv
- RVFI ports are added to ariane module
- rvfi_tracer.sv is a module added in ariane-testharness.sv
- RVFI_TRACE enables RVFI trace generation
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Move example_tb from cva6 to core-v-verif project
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile: remove useless rule for vsim
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add timescale definition when vsim is used
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add vcs support (fix #570 )
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* rvfi_tracer.sv: fix compilation error raised by vcs
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: use only 2 threads for verilator
when using 4 threads, tests from riscv-compliance and riscv-tests
test suite are randomly stucked with rv32ima configuration
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Flist.cva6: cleanup for synthesis workflow
Thales synthesis workflow does not manage comments at end of lines
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Support FPGA generation
- ariane_xilinx.sv: fix AXI bus expansion
- .gitignore, Makefile, run.tcl: fix paths
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* riscv-dbg: update to 989389b0 (to support 32-bit CVA6 debug)
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Create cva6_config_pkg to setup 32- or 64-bit configuration
According to selected configuration, Makefile calls
cv32a6_imac_sv0_config_pkg.sv or cv64a6_imac_sv39_config_pkg.sv
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Flist, ariane_wrapper.sv: add wrapper to expand rvfi and axi structures
needed for dc_shell
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* cv*a6_*_pkg.sv, riscv_pkg.sv: (Fix) Use the camel case for the localparams
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* riscv_pkg.sv: clean-up the cva6_config_pkg import
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile, ariane.sv: RVFI_TRACE define conditions RVFI port in ariane
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Add lfsr.sv to manifest
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* Directory re-organzation
* fpga/xilinx/xlnx_axi_dwidth_converter_dm_*: move files (#726 )
into the new file organisation
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* move mmu_sv32 and mmu_sv39, move bootrom, update path (#729 )
Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com>
Co-authored-by: Mike Thompson <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Co-authored-by: sébastien jacq <57099003+sjthales@users.noreply.github.com>
2021-09-24 17:21:19 +02:00
