André Sintzoff
|
a3372c51f0
|
cva6_rvfi_probes.sv: fix be5ac20e4 (PR 2749) (#2751)
bender-up-to-date / bender-up-to-date (push) Has been cancelled
ci / build-riscv-tests (push) Has been cancelled
ci / execute-riscv64-tests (push) Has been cancelled
ci / execute-riscv32-tests (push) Has been cancelled
rs1_i and rs2_i have XLEN width
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
|
2025-01-29 15:50:34 +01:00 |
|
JeanRochCoulon
|
be5ac20e46
|
Fix RVFI rs1/rs2 len from VLEN to XLEN (#2749)
bender-up-to-date / bender-up-to-date (push) Waiting to run
ci / build-riscv-tests (push) Waiting to run
ci / execute-riscv64-tests (push) Blocked by required conditions
ci / execute-riscv32-tests (push) Blocked by required conditions
RVFI rs1 and rs2 operands were VLEN, it has been fixed to be XLEN.
|
2025-01-28 18:37:07 +01:00 |
|
Guillaume Chauvon
|
98604b5920
|
csr_regfile: SEIP is read only 0 (fix #2056) (#2716)
Fix #2056
---------
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
|
2025-01-21 14:53:37 +01:00 |
|
Côme
|
4df49a6b0f
|
superscalar: make SuperscalarEn a CVA6Cfg attribute (#2322)
|
2024-07-05 14:09:48 +02:00 |
|
Côme
|
96ae8ed223
|
superscalar: allow speculative instructions (#2278)
|
2024-06-20 15:55:56 +02:00 |
|
Côme
|
eac60af1a9
|
superscalar: add a second issue port (#2209)
|
2024-06-09 20:47:09 +02:00 |
|
Côme
|
779927485d
|
superscalar: duplicate decode stage (#2077)
|
2024-04-26 12:09:42 +02:00 |
|
JeanRochCoulon
|
527a989542
|
Clean-up 65x config_pkg.sv file by removing the localparams (#2031)
|
2024-04-11 11:29:31 +02:00 |
|
MarioOpenHWGroup
|
62bdf11594
|
Bump core-v-verif d94f0de and fix questa simulator (#1915)
|
2024-03-21 19:02:41 +01:00 |
|
Côme
|
bd4b57cc64
|
Parametrization step 3 part 3 (last) (#1940)
|
2024-03-18 16:19:52 +01:00 |
|
Côme
|
4817575de9
|
Parametrization step 3 part 2 (#1939)
|
2024-03-18 12:06:55 +01:00 |
|
Côme
|
987c645bb7
|
Parametrization step 3 (#1935)
This is the third step for #1451. Many values are moved but not all values are moved yet
* move NR_SB_ENTRIES & TRANS_ID_BITS
* remove default rvfi_instr_t from spike.sv
* fifo_v3: ariane_pkg::FPGA_EN becomes a param
* move FPGA_EN
* inline wt_cache_pkg::L15_SET_ASSOC
* move wt_cache_pkg::L15_WAY_WIDTH
* inline wt_cache_pkg::L1I_SET_ASSOC
* inline wt_cache_pkg::L1D_SET_ASSOC
* move wt_cache_pkg::DCACHE_CL_IDX_WIDTH
* move ICACHE_TAG_WIDTH
* move DCACHE_TAG_WIDTH
* move ICACHE_INDEX_WIDTH
* move ICACHE_SET_ASSOC
* use ICACHE_SET_ASSOC_WIDTH instead of $clog2(ICACHE_SET_ASSOC)
* move DCACHE_NUM_WORDS
* move DCACHE_INDEX_WIDTH
* move DCACHE_OFFSET_WIDTH
* move DCACHE_BYTE_OFFSET
* move DCACHE_DIRTY_WIDTH
* move DCACHE_SET_ASSOC_WIDTH
* move DCACHE_SET_ASSOC
* move CONFIG_L1I_SIZE
* move CONFIG_L1D_SIZE
* move DCACHE_LINE_WIDTH
* move ICACHE_LINE_WIDTH
* move ICACHE_USER_LINE_WIDTH
* move DCACHE_USER_LINE_WIDTH
* DATA_USER_WIDTH = DCACHE_USER_WIDTH
* move DCACHE_USER_WIDTH
* move FETCH_USER_WIDTH
* move FETCH_USER_EN
* move LOG2_INSTR_PER_FETCH
* move INSTR_PER_FETCH
* move FETCH_WIDTH
* transform SSTATUS_SD and SMODE_STATUS_READ_MASK into functions
* move [SM]_{SW,TIMER,EXT}_INTERRUPT into a structure
* move SV
* move vm_mode_t to config_pkg
* move MODE_SV
* move VPN2
* move PPNW
* move ASIDW
* move ModeW
* move XLEN_ALIGN_BYTES
* move DATA_USER_EN
* format: apply verible
|
2024-03-15 17:21:34 +00:00 |
|
Côme
|
aed4ed7c23
|
move functions into modules (#1926)
|
2024-03-13 17:46:33 +01:00 |
|
Côme
|
83d94bbb69
|
transform rvfi types into macros (#1921)
|
2024-03-12 17:34:27 +01:00 |
|
Côme
|
32a3cd56ee
|
Parametrization step 2 (#1908)
|
2024-03-08 22:53:42 +01:00 |
|
Yannick Casamatta
|
bc41a0b7fb
|
Modify rvfi probes for param change (#1900)
|
2024-03-07 18:34:27 +01:00 |
|
Yannick Casamatta
|
1dec79464e
|
add csr in rvfi (#1833)
|
2024-02-24 00:10:23 +01:00 |
|
Yannick Casamatta
|
0ce6b40b26
|
Remove all logic and sequential related to RVFI in CORE cva6 (#1762)
|
2024-01-18 22:51:10 +01:00 |
|