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Author	SHA1	Message	Date
Florian Zaruba	04902ce01e	🚧 Remove dm_ctrl and move logic to dm_memory	2018-07-12 17:36:14 -07:00
Florian Zaruba	54bbced94f	✨ Add debug hart ctrl memory interface	2018-07-11 16:25:49 -07:00
Florian Zaruba	82c06d0292	✨ Add debug ROM	2018-07-11 14:56:25 -07:00
Florian Zaruba	d848f7f2fd	🐛 Fix capability of debugging from first instruction	2018-07-10 16:02:19 -07:00
Florian Zaruba	1b01715fc7	✨ Add SiFive debug rom	2018-07-10 16:01:53 -07:00
Florian Zaruba	d4a1d7e616	Implement debug instruction and CSR in tracer	2018-07-10 14:36:01 -07:00
Florian Zaruba	f501291661	✨ Add first-stage bootloader	2018-07-10 14:25:35 -07:00
Florian Zaruba	8700b04af9	Add bootrom sw from rocket-core	2018-07-10 12:00:41 -07:00
Florian Zaruba	1f7244e1a0	🚧 Instantiate Hart Ctrl	2018-07-10 11:35:12 -07:00
Florian Zaruba	eb95474ace	🐛 Minor fixes to hart enumeration logic	2018-07-10 10:29:47 -07:00
Florian Zaruba	527e944577	🚧 Verilator debug integration	2018-07-10 09:20:07 -07:00
Florian Zaruba	5b45929af6	✨ Add dscratach0 CSR	2018-07-10 09:18:28 -07:00
Florian Zaruba	139a34df2f	🔥 Remove debug unit	2018-07-09 16:30:57 -07:00
Florian Zaruba	4c79fd39c2	🚧 Adapt debug ctrl interface	2018-07-09 16:26:52 -07:00
Florian Zaruba	ba32f7c926	🚧 Re-name debug module files	2018-07-02 16:05:48 -07:00
Florian Zaruba	b79a8b6e9a	🚧 Add missing debug CSRs	2018-07-02 16:03:21 -07:00
Florian Zaruba	cf431ee491	🚧 Add debug CSRs to DM	2018-06-30 18:51:23 -07:00
Florian Zaruba	e942c2052b	♻️ Re-factor packages and add debug pkg	2018-06-30 16:51:54 -07:00
Florian Zaruba	f2cca400af	✨ Add return to debug when ebreak detected	2018-06-30 15:23:50 -07:00
Florian Zaruba	8199995c20	🎨 Update CHANGELOG and CONTRIBUTING	2018-06-30 14:19:23 -07:00
Florian Zaruba	9842feb032	✨ Implement core-debug features	2018-06-30 14:12:22 -07:00
Florian Zaruba	6eb6c89ee5	Add dret instruction and implement debug mode	2018-06-30 12:08:38 -07:00
Florian Zaruba	9d1218529e	Make icache bypass-able	2018-06-30 19:27:40 +02:00
Florian Zaruba	5fb6f920d3	🏗️ Add debug CSRs	2018-06-28 09:30:00 +02:00
Florian Zaruba	d18c7d9848	🔥 Remove legacy debug	2018-06-28 08:47:37 +02:00
Florian Zaruba	d03ed66e9d	🐛 Fix problem with incorrect wiring	2018-06-28 08:43:42 +02:00
Florian Zaruba	ef57bee7be	Merge branch 'master' into ariane_next	2018-06-20 18:59:20 +02:00
Florian Zaruba	78e6408e8e	Fix compile time issue with VCS #20	2018-06-20 18:54:03 +02:00
Florian Zaruba	35105da734	Fix compile time issue with VCS #20	2018-06-20 18:52:22 +02:00
Florian Zaruba	2f4b412d20	🐛 Fix bug violating AXI protocol	2018-06-14 14:35:59 -07:00
Florian Zaruba	eee88d1a25	Merge branch 'ariane_next' of github.com:pulp-platform/ariane into ariane_next	2018-06-14 23:32:37 +02:00
Florian Zaruba	c946a2e1b2	Fix issue #44	2018-05-22 14:21:59 +02:00
Florian Zaruba	7d3f945fba	Fix issue #44	2018-05-22 14:10:06 +02:00
Stefan Mach	c3a4caad8a	✨ Add register renaming to issue stage ... Renaming can be turned on or off with the `ENABLE_RENAME` parameter in `ariane_pkg.sv`.	2018-05-06 18:19:41 +02:00
Florian Zaruba	46399072da	Update block diagram	2018-05-06 16:43:53 +02:00
Florian Zaruba	ae174ca6c3	🐛 Fix problem with I$ when axi.last is high	2018-04-22 19:18:20 +02:00
Florian Zaruba	4d1a480872	♻️ Move flush logic to end of divider FSM	2018-04-12 17:40:44 +02:00
Florian Zaruba	98516bb131	Merge branch 'raulbehl-master'	2018-04-12 17:37:24 +02:00
Florian Zaruba	9d55560fd5	Merge branch 'master' of git://github.com/raulbehl/ariane into raulbehl-master	2018-04-12 17:36:47 +02:00
Florian Zaruba	e4d8c2491b	Merge branch 'master' into ariane_next	2018-04-11 16:52:10 +02:00
Matheus Cavalcante	aaea06eba0	Reset cache_ctrl state after a kill_req_i (#38)	2018-04-11 10:14:42 +02:00
Florian Zaruba	7b0a436d70	Pump tb version	2018-04-09 15:33:40 +02:00
Florian Zaruba	bd9e852596	Merge branch 'master' into ariane_next	2018-04-09 15:18:45 +02:00
Florian Zaruba	62fc4bd816	Pump submodules, cherry-pick TLB clean-up	2018-04-09 15:11:15 +02:00
Florian Zaruba	a063c7f6fa	Merge pull request #35 from suehtamacv/master ... Fix #34	2018-04-09 14:23:38 +02:00
Matheus Cavalcante	f606310701	Fix D$ behaviour during a flush	2018-04-09 13:14:15 +02:00
raulbehl	80aa8534e3	Code updates for #26 after review ... - Updated logic to clear mul/div valid for clearing the pipelined valid signal - Added logic in DIV FSM to reset to IDLE whenever flush_i is asserted	2018-03-24 23:52:44 +05:30
Florian Zaruba	7210b48c28	Merge branch 'lowRISC-pmpcfg'	2018-03-21 19:40:24 +01:00
Jonathan Richard Robert Kimmitt	7f95cbb0fc	Add travis pre-check script and remove spurious spaces from Makefile	2018-03-21 16:58:53 +00:00
Jonathan Richard Robert Kimmitt	e20dd9de2a	Add placeholders for PMP CSRs for memory protection.	2018-03-21 15:19:37 +00:00