* Added support for Xilinx Kintex-7 FPGA KC705 Evaluation Kit
* Added better handling for the board parameter with the genesys2 as a default. Bumped the ariane-ethernet repo for compatibility
* Add spike isa sim
* Fix AMO problem in verilator
* 🎨 Tidy up FPU wrapper
* Bump axi_exclusive submodule
* Refactor serpent AXI adapter, bump dbg and atomics submodules, add separate bootrom for linux on OpenPiton (#190)
* Refactor serpent AXI adapter
* Disable FPU in OpenPiton by default
* Bump dbg and atomics submodules
* Fix cache testbenches (interface change)
* FPGA bootrom changes for OpenPiton SDHC
* Introduce two bootroms, one for baremetal apps (pitonstream), and one for linux boot from SD
* Testing barrier-based synchronisation instead of CLINT-based
* This bootrom works for 2 core on g2 and if you change MAX_HARTS to 4, then 4 cores on vc707
* Add MAX_HARTS switch to makefile
* Fix gitlab CI
* Revert standard FPGA bootrom
* Update Flist
* Make UART_FREQ a parameter
* Fix typo in tb.list and an error in define switch in ariane_pkg
* Copy over SD-driver in bootloader from @leon575777642
* Fix compilation issues of bootrom
* Change signal name in serpent periph portlist
* Correct generate statement in serpent dcache memory
* Add Piton SD Controller, FPGA fixes
* Fix race condition in dcache misshandler
* Add tandem spike to Make flow
* Remove OpenPiton SD Card controller again
* Change reset strategy in ariane_verilog_wrap.sv, remove unneeded sigs in serpent_peripherals.
* saving...
* ⬆️ Updates for new FPU
* Add sv fpu to FPGA flow
* Use multi-threading capabilities of verilator
- Deactivate non-standard floating point arguments
- Make multi-threading conditional on the availability of verilator 4
* Remove DPI threadsafety
* Reduce FPGA clock frequency
- Remove couple of -v- tests to reduce test-time
* Fix documentation and fpga flow
- Fix cycle time to accommodate FPU
- Fix FPGA constraints
* Change UART frequency
