* Clean-up README.md and top-level directory
This removes the duplicate `scripts` and `util` directories. Furthermore
the README is condensed by collapsing the citation and adding the
CITATION file to the repository.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
* Re-name icache req/rsp structs
The structs used to communicate with the icache have contained the
direction, which makes no sense for structs since they inherently don't
have any direction.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
---------
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
* Clarify scope of Verilator model
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* Update repo user docs
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* Update repo user docs
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* CORE-V not COREV
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* Summary: initial dromajo integration
* some changes to Makefile to enable `make verilate DROMAJO=1`
* adding ifdefs to ariane_tb.cpp to disable HTIF
* adding dromajo repo
* making dromajo repo a submodule
* syncing with upstream
* bumping to the latest dromajo commit
* Summary: adding DPI functions for cosim
* added new file tb/dpi/dromajo_cosim.cc that contains
all DPIs for dromajo to work
* editted Makefile to see the above file
* Summary: fixing build issues
* fixing syntax errors in dpi file
* renaming dpi file due to name conflict with shared library
* fixing path in Makefile to the shared dromajo lib
* bumping to the latest dromajo change
* Summary: loading checkpoint to bootrom
This change adds `+checkpoint=` argument to the verilator simulator
as well as corresponding changes to load the dromajo checkpoint into
the bootrom. Dromajo checkpoint bootcode contains series of csrw and
immediate loads to restore the architectural state of the processor.
dromajo_bootrom.sv
is a copy of a generated bootrom.sv file. This
file parses the verilog plusargs and loads the bootrom with the code
that is pointed by the +checkpoint.
csr_regfile.sv
Dromajo needs to start running the code in debug mode. The default
value of debug_mode_q was changed to 1.
* updating dromajo to the latest change
* Summary: sync main memories of dromajo and ariane
These changes load the checkpoint into the main memory of Ariane.
The checkpointed memory that is dumped from dromajo contains
(1) the binary and (2) the values of all stores that dromajo
globally performed before dumping the checkpoint.
dromajo_ram.sv
This file is a copy of SyncSpRamBeNx64.sv and was modified to parse
+checkpoint argument to load the memory from the path pointed by
the argument.
The remaining changes were introduced to instantiate the above file
when DROMAJO=1 flag is set.
* Summary: calling DPIs for cosimulation
This change introduces the calls to DPI functions that interface
with Dromajo.
* updating to the latest commit of dromajo
* disabling verbose output when preloading bootrom and mainram
* Summary: bug fix - update logic of `dcsr_d.prv`
This change was made per discussion with Florian via email. The
current versionincorrectly implements the update logic of
`dcsr_d.prv`.
The confusion came from the fact that the core should update its
`dcsr_d.prv` to the current running privilege level when entering
debug mode. I've attached a patch which, as you suggested, removes
the wrong update logic in the CSR write process and should now
correctly handle the update when entering debug mode
(4.9.1 Debug Control and Status of the debug specification).
* bump to the latest version of dromajo
* Summary: dromajo DPI change
This change:
* Ariane doesn't commit ebreaks and ecalls so some workaround
was encorporated
* Proper exit(0) on cosim pass
* Summary: support for running binaries with dromajo
This change adds the ability to run the following command:
`make run_dromajo BIN=\path\to\riscv\bin`
It automates the dromajo's checkpoint creation and runs the binary
on Ariane with dromajo cosimulation.
For this to work Ariane must be build with DROMAJO=1.
* changing dromajo recipe name to be consistent with existing names
* adding instructions on how to run cosim with dromajo
* Bump to release 0.6.2
* added license headers
* added more details about dromajo
* Add spike isa sim
* Fix AMO problem in verilator
* 🎨 Tidy up FPU wrapper
* Bump axi_exclusive submodule
* Refactor serpent AXI adapter, bump dbg and atomics submodules, add separate bootrom for linux on OpenPiton (#190)
* Refactor serpent AXI adapter
* Disable FPU in OpenPiton by default
* Bump dbg and atomics submodules
* Fix cache testbenches (interface change)
* FPGA bootrom changes for OpenPiton SDHC
* Introduce two bootroms, one for baremetal apps (pitonstream), and one for linux boot from SD
* Testing barrier-based synchronisation instead of CLINT-based
* This bootrom works for 2 core on g2 and if you change MAX_HARTS to 4, then 4 cores on vc707
* Add MAX_HARTS switch to makefile
* Fix gitlab CI
* Revert standard FPGA bootrom
* Update Flist
* Make UART_FREQ a parameter
* Fix typo in tb.list and an error in define switch in ariane_pkg
* Copy over SD-driver in bootloader from @leon575777642
* Fix compilation issues of bootrom
* Change signal name in serpent periph portlist
* Correct generate statement in serpent dcache memory
* Add Piton SD Controller, FPGA fixes
* Fix race condition in dcache misshandler
* Add tandem spike to Make flow
* Remove OpenPiton SD Card controller again
* : Fix PITON_ARIANE define issues
* Fix write-back / cache read collision issue in serpent dcache.
* Add separate bootrom / device tree for openpiton (hardcoded for 1x1 tile config at the moment).
* Bootrom generation update (better compatibility with older python versions), new bootrom for OpenPiton+Ariane.
* Fix assertion in icache.
* Correct JTAG timing constraints.
* Fix parameter type in fpga toplevel (fix#168).
* Remove conflicting bootrom from fpga file list.
* This flushs the branch predictors when entering exception handlers in order to avoid speculative fetches from virtual addresses (to be improved with PMAs).
* Fix byte offset of IPIs in CLINT
* Disable DCache flushes on fence for write-through cache (not needed in that case)
* Fix blocking assignments in ff process.
* Fix register access issue in debug mode, only affects A0 (fix#179).
* Fix multiple driver issue in PLIC
* Do not assume replicated data in serpent dcache when reading from an NC region.
* Another byte offset fix in IPIs (CLINT)
* Add AXI64 compliance switch to dcache_mem
* Fix genesys 2 constraints
* Map serpent atomic requests onto AXI atomic/exclusive transactions.
* Cleanup of AXI memory plumbing, add separate AXI adapter module.
* Remove unneeded interface signals, increase wbuffer #pending tx
* Fix verilator compilation issues in AXI adapter.
* Delete unnecessary constraint
* Delete duplicate module instance
* Update gitlab CI script
* Small fixes to make riscv atomics work with serpent_axi_adapter.
* Update travis and gitlab-ci scripts
* Register b responses for better timing.
* Remove fpu div submodule, update Makefile paths and src lists
* Constant bits in haltsum reduction must be 1 (AND reduction).
* Switch to DTM from riscv-dbg submodule
* Further cleanup fixes in AXI/serpent atomics
* Bump riscv-dbg version
* Change reset strategy in ariane_verilog_wrap.sv, remove unneeded sigs in serpent_peripherals.
* saving...
* ⬆️ Updates for new FPU
* Add sv fpu to FPGA flow
* Use multi-threading capabilities of verilator
- Deactivate non-standard floating point arguments
- Make multi-threading conditional on the availability of verilator 4
* Remove DPI threadsafety
* Reduce FPGA clock frequency
- Remove couple of -v- tests to reduce test-time
* Fix documentation and fpga flow
- Fix cycle time to accommodate FPU
- Fix FPGA constraints
* Change UART frequency
