github-mirrors/cva6 - Blizzard Finnegan's Codeforge

mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-19 11:54:46 -04:00

Author	SHA1	Message	Date
AngelaGonzalezMarino	db088159eb	Mmu design document (#2117 )	2024-06-17 09:23:44 +02:00
slgth	802066bfd3	docs: move riscv-isa-manual outside of cv32a65x documentation (#2264 )	2024-06-16 23:20:41 +02:00
JeanRochCoulon	7e8e2c931f	Fix CSR chapter insertion and rename Design Doc names (remove "for cv32a65x") (#2262 )	2024-06-14 15:39:22 +02:00
CoralieAllioux	205872acc6	Fix initialization of memory array in simulation (#2259 )	2024-06-14 14:34:08 +02:00
CoralieAllioux	3ed5e78c91	[Xcelium flow] xrun testharness rules (#2223 )	2024-06-14 14:31:56 +02:00
Jalali	212c14e4b4	CSR verification : modify coverage based on new specification (#2261 )	2024-06-14 14:01:23 +02:00
JeanRochCoulon	d83b3f6ffd	Execute SpyGlass lint job only when RTL is modified (#2255 )	2024-06-14 09:19:06 +00:00
Mathieu Gouttenoire	3d00079c19	Prepare for LLVM (#2251 )	2024-06-14 11:12:03 +02:00
AbdessamiiOukalrazqou	3fccfba900	[gen_from_riscv_config]modify csr updater.py /fix-2191 , modify csr_updater.yaml (#2258 )	2024-06-14 10:51:37 +02:00
slgth	e3943f5913	cv64a6_mmu: set NrPMPEntries to 16 (fixes #2244 ) (#2248 )	2024-06-14 10:05:35 +02:00
JeanRochCoulon	cb6211bbb8	Remove cv32a6_embedded configuration (#2246 )	2024-06-14 08:30:17 +02:00
JeanRochCoulon	e26267b220	[HOT FIX] fix synthesis job (#2256 ) Fix read_section_sv type	2024-06-14 08:26:06 +02:00
Asmaa Kassimi	77264cd572	add spyglass waiver file to waive ErrorAnalyzeBBox error (#2254 )	2024-06-13 16:54:54 +02:00
André Sintzoff	105d3601b6	update riscv-isa-manual to riscv-isa-release-c8c8075-2024-06-12 (#2253 )	2024-06-13 16:45:04 +02:00
AngelaGonzalezMarino	8164828913	Fix instruction realign when C extension is not used (#2241 )	2024-06-13 11:17:25 +02:00
slgth	b1850a8cb7	docs: fix spec_builder.py (#2249 )	2024-06-12 20:07:22 +02:00
André Sintzoff	361b17e7b0	cv32a65x doc: fix RISC-V unpriv pdf generation issue introduced in `718c4e23` Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>	2024-06-12 11:32:36 +02:00
André Sintzoff	d5b7cc77ff	cv32a65x doc: split unpriv and priv HTML pages Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>	2024-06-12 11:18:31 +02:00
Coralie Allioux	6c0cf186fc	Fix ALL_SIMV_UVM_FLAGS auto-merge	2024-06-12 11:16:18 +02:00
Coralie Allioux	2c48fccb52	Remove unused variables	2024-06-12 11:16:18 +02:00
Coralie Allioux	fa2a676007	Fix incdir for uvme and uvmt + fix dpi lib	2024-06-12 11:16:18 +02:00
isabelle schmid	36098bf827	Correct uvme and uvmt path	2024-06-12 11:16:18 +02:00
isabelle schmid	fa9a36860c	Add xrun-testharness support	2024-06-12 11:16:18 +02:00
Coralie Allioux	27aab922b9	Fix tohost_addr: RISCV bin must be more generic	2024-06-12 11:16:18 +02:00
isabelle schmid	4e2baff507	Fix tohost_addr and xrun flags	2024-06-12 11:16:18 +02:00
isabelle schmid	dec70a18c5	Make it compliant with new DPI build	2024-06-12 11:16:18 +02:00
isabelle schmid	db6e0c9696	Add xcelium flow	2024-06-12 11:16:18 +02:00
isabelle schmid	c36837142f	Add xrun-testharness	2024-06-12 11:01:15 +02:00
isabelle schmid	27836559ae	Add xrun-uvm options	2024-06-12 11:01:15 +02:00
CoralieAllioux	28e94e5ce3	[Xcelium flow] Clean DPI void function import (#2222 )	2024-06-12 09:45:33 +02:00
CoralieAllioux	367fe5850a	[Xcelium flow] corev dv yaml (#2210 )	2024-06-12 09:44:44 +02:00
Akiho Kawada	bc7149adc7	refactor hpdcache_cache_subsystem module code to ease reutilization (#2173 )	2024-06-11 23:12:30 +02:00
slgth	f57a6c0106	Move CV32A65X documentation into its own chapter (#2236 )	2024-06-11 18:01:25 +02:00
JeanRochCoulon	4391fc4b14	Use cv32a6_imac_sv32 to generate FPGA bitstream (#2229 )	2024-06-11 16:25:07 +02:00
André Sintzoff	546a8c26da	csr_regfile.sv: if no U-mode, mstatus.tw is read-only 0 (fix #2228 ) (#2233 )	2024-06-11 15:08:28 +02:00
JeanRochCoulon	91871d97f3	Update functionality.rst (#2235 )	2024-06-11 12:31:52 +02:00
JeanRochCoulon	2266f75f2d	MTVAL is read-only zero when TvalEn = 0 (#2231 )	2024-06-11 11:22:41 +02:00
JeanRochCoulon	9d02734bd1	Fix PMPCFG number (from 8 to 4, from which 2 are read-only zero) (#2232 )	2024-06-11 11:15:27 +02:00
André Sintzoff	afb3265296	csr_regfile.sv: if no U-mode, mcounteren does not exist (fix #2221 ) (#2227 )	2024-06-10 21:42:00 +02:00
JeanRochCoulon	7ccf82ce76	Add param to enable/disable Zihpm and Zicntr extensions for 65x (#2208 )	2024-06-10 15:14:03 +02:00
JeanRochCoulon	dc000d6c37	Define a new param to constraint mtvec to be in direct mode only (#2226 )	2024-06-10 11:59:54 +00:00
Jalali	feb35f2b88	Fix Csr instruction decode and change the message verbosity (#2225 )	2024-06-10 13:22:05 +02:00
Côme	eac60af1a9	superscalar: add a second issue port (#2209 )	2024-06-09 20:47:09 +02:00
dependabot[bot]	424eca6f63	Bump verif/core-v-verif from `b92d30f` to `835720b` (#2215 )	2024-06-09 20:40:00 +02:00
Mathieu Gouttenoire	ade4c85e13	Remove extra -v in smoke-tests.sh (#2207 )	2024-06-06 16:51:17 +02:00
Zbigniew Chamski	592487ffa0	[riscv-config] Align CV32A65X spec on adoc, cleanup defs. Fix CSR updater. (#2206 )	2024-06-06 11:19:41 +02:00
Jalali	278649d3ed	Update coverage script after exclude HPDcache module (#2197 )	2024-06-05 09:55:48 +02:00
Jalali	35255e1c47	Exclude HPD cache module from code coverage (#2194 )	2024-06-04 23:30:36 +02:00
Zbigniew Chamski	aa76752f18	Update riscv-config infra to better match expressivity needs of CV32A65X. (#2193 )	2024-06-04 18:12:14 +02:00
MarioOpenHWGroup	721fa0c175	Fix Github CI by changing riscv-isa-sim hash (#2190 )	2024-06-04 12:33:21 +02:00

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7004 commits