* add axi parameters to cfg
* Move axi_intf.sv from core to corev_apu
* Move ariane_axi_pkg.sv from core to corev_apu
* Merge axi and l15 into noc
* Fixes to build and run openpiton
---------
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jonathan Balkind <jbalkind@ucsb.edu>
Support Ara via a custom, parametrised accelerator interface.
cv64a6_imafdcv_sv39_config_pkg.sv enables V extension
Pre-processor constant ARIANE_ACCELERATOR_PORT enables the interface between CVA6 and Ara.
FPU is bumped to a SIMD-compatible version
Backwards compatibility should be preserved. Once this is merged, we will change the reference of Ara upstream CVA6.
-----
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Co-authored-by: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
Co-authored-by: Matteo Perotti <mperotti@iis.ee.ethz.ch>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
* wb_dcache: Forward "atomic transactions" to AXI
* Correct bugs
* Forward LR/SC atomics
* Fix CI
* miss_handler: Route AMO port through arbiter
* axi_adapter: Correct LOAD AMOs handling
Accept read data only after (or together) handshake on B channel
* Restore old ID
* Correct atop encodings
* Correct AMOs AXI ID
* Correct wb_dcache testbench
Previously not comparing AMOs at all! Due to amo_exp_resp being 'x
* Realign and sign extend 32b request rdata
* Use axi_pkg definitions for ATOPs encoding
* Remove whitespace
* wb_dcache: Style corrections
Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
- Fix the AXI ID width for the CLINT (previously `4`, now `5`)
- Parametrise the CLINT's AXI types
- Deprecate `axi_[master|slave]_connect` and move to AXI assign macros,
as they allow arbitrary AXI types
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
* Change questa version reference format
* bump common_cells to v1.23
* Bump axi to v0.31.0, replace axi_node with axi_xbar
* Bump register_interface for axi compatibility
* add prot signals to axi_lite for compatibility
* Makefile: Implement the plateforms defined in cva6 specification
target variable can take cv64a6_imacfd_sv39, cv32a6_imac_sv0,
cv32a6_imac_sv32, cv32a6_imacf_sv32
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Fix plateform name: from imacfd to imafdc
from imacf to imafc
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
*_slv_t types are needed only in ariane_testharness.
The CVA6 core should not depend on packages related to the SoC
where it is placed.
Signed-off-by: Luca Zulberti <zulberti.luca@gmail.com>
- add wrapper module to connect wt_icache to AXI bus
- replace std_icache by cva6_icache_axi_wrapper
- rename wt_icache to cva6_icache
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Add a register file, optimized for synthesis on FPGAs supporting
distributed RAM.
Principle:
The baseline implementation implements the register file as an array of
flip-flops and implements large multiplexers for read- and write-
accesses. On FPGAs, we have a more efficient implementation for data
storage: By using distributed RAM for memory storage, we can store up
to 64 bits in just one LUT (depending on the memory layout and FPGA
device). In addition, distributed RAM comes with integrated address
decoders. The register file features one distributed RAM block per
implemented sync write port, each with the parametrized number of
async read ports. The read access is arbitrated depending on which
block was last written to. For this purpose an additional array of
*NUM_WORDS* registers is maintained keeping track of write accesses.
Since both FFs and multiplexers are an expensive structure on FPGA
technology, the achieved savings are considerable. The register file
is used for the FPU and general purpose register files.
Concrete Savings: (Xilinx Kintex-7, xc7k325tffg900-2)
```
LUT FF LUTRAM
---------------------------------
baseline: 40499 22799 0
optimized: 36350 18806 440
---------------------------------
Diff -4149 -3993 +440
-10.2% -17.5%
```
Signed-off-by: ganoam <gnoam@live.com>
* enable exp_backoff for LR/SC
also changed to check LR instead of checking SC.
* add exp_backoff module in
* Add exp_backoff in Bender.yml
* add exp_backoff in Makefile src list
* : Fix PITON_ARIANE define issues
* Fix write-back / cache read collision issue in serpent dcache.
* Add separate bootrom / device tree for openpiton (hardcoded for 1x1 tile config at the moment).
* Bootrom generation update (better compatibility with older python versions), new bootrom for OpenPiton+Ariane.
* Fix assertion in icache.
* Correct JTAG timing constraints.
* Fix parameter type in fpga toplevel (fix#168).
* Remove conflicting bootrom from fpga file list.
* This flushs the branch predictors when entering exception handlers in order to avoid speculative fetches from virtual addresses (to be improved with PMAs).
* Fix byte offset of IPIs in CLINT
* Disable DCache flushes on fence for write-through cache (not needed in that case)
* Fix blocking assignments in ff process.
* Fix register access issue in debug mode, only affects A0 (fix#179).
* Fix multiple driver issue in PLIC
* Do not assume replicated data in serpent dcache when reading from an NC region.
* Another byte offset fix in IPIs (CLINT)
* Add AXI64 compliance switch to dcache_mem
* Fix genesys 2 constraints
* Map serpent atomic requests onto AXI atomic/exclusive transactions.
* Cleanup of AXI memory plumbing, add separate AXI adapter module.
* Remove unneeded interface signals, increase wbuffer #pending tx
* Fix verilator compilation issues in AXI adapter.
* Delete unnecessary constraint
* Delete duplicate module instance
* Update gitlab CI script
* Small fixes to make riscv atomics work with serpent_axi_adapter.
* Update travis and gitlab-ci scripts
* Register b responses for better timing.
* Remove fpu div submodule, update Makefile paths and src lists
* Constant bits in haltsum reduction must be 1 (AND reduction).
* Switch to DTM from riscv-dbg submodule
* Further cleanup fixes in AXI/serpent atomics
* Bump riscv-dbg version
* Fix latch and timing loop in debu_req
* Fix unconnected IPI signals in CLINT, and unconnected regs in CSR_REGFILE
* Fix several issues with AXI IDs in axi_adapter, add AXI ID width parameter, and assertions testing for invalid read/write data
* Eliminate sim, simc make targets for Questa. Tests can be directly invoked via typing name and optionally specifying the gui-mode.
* Initialize instruction traced shadow regfile to zero at start of simulation
Fix progbuf offsets and tie unsupported counters to zero to avoid propagation of X
Fix printouts of assertions
Modify bootrom to prevent assignment of X to output
* Make separate CI target for AMO tests
* Bump fpga-support version
* Add AMO tests list
* Fix FPU submodule version
* Change core_id + cluster_id into hart_id
* Rename gitlab CI tests
* Replace all SYNTHESIS macros with pragma translate_off
* Update readme, bump common cells, benderize
* Fix torture make target
* Remove unneeded signal
