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893 commits

Author SHA1 Message Date
Rose Thompson
33a10fd017 Creating separate test for instruction misaligned page fault. 2025-05-07 16:26:26 -05:00
Rose Thompson
1d80bd1abf New test for spilled store page fault. ImperasDV indicates Wally does not improve the correct mtval. 2025-05-07 10:53:36 -05:00
David Harris
90b4337a49 Support PMP granularity G > 0 in PMP registers 2025-05-05 15:29:30 -07:00
Rose Thompson
048fa377ca Created a new test which reproduces the same error as the zsh bug, github issue #1263. 2025-05-05 00:41:10 -05:00
Rose Thompson
cb3d3d9913 Updated author. 2025-05-04 12:24:34 -05:00
Rose Thompson
29f86bb5cb Test forces the EBU to have a partially overlapping IFU and LSU request. The LSU request occurs duing an ongoing IFU request. 2025-05-04 12:20:18 -05:00
Rose Thompson
9407bf1f89 Merge branch 'main' of github.com:rosethompson/cvw 2025-05-04 11:33:38 -05:00
David Harris
d2b3ae0a96 Commented timer initialization 2025-05-04 08:39:05 -07:00
David Harris
d22cd248c7 Fixed mismatch with ImperasDV by adding sfence.vma after changing menvcfg.PBMTE per privileged spec 3.1.18 2025-05-03 07:10:43 -07:00
Rose Thompson
3f69cffdf8 Getting close to making this hptw ifu cache interaction test work. 2025-04-29 14:54:34 -05:00
Rose Thompson
cd0b44dd8b Cleaned up ebuArb test. 2025-04-27 13:18:52 -05:00
Rose Thompson
bcf81e5aad Created test to force ebu arbitration. 2025-04-27 13:13:24 -05:00
Jordan Carlin
a7345778c0
Update rv32 2025-04-23 11:33:40 -07:00
Jordan Carlin
9f607e20d9
Fix data segment in WALLY-TEST-LIB-64 2025-04-23 11:31:36 -07:00
David Harris
9a46061716 100% coverage tlbcontrol 2025-04-18 19:15:07 -07:00
Corey Hickson
9bc3c7c78c Undo unnecessary tests/coverage additions 2025-04-17 08:09:14 -07:00
Corey Hickson
7c5a5c592c Full decomp code coverage 2025-04-17 03:06:38 -07:00
Corey Hickson
6c651cd73e Full cacheways code coverage 2025-04-17 02:28:20 -07:00
Corey Hickson
f7bc15eb3e Full priv code coverage 2025-04-17 02:05:35 -07:00
David Harris
42f78c645b
Merge pull request #1363 from coreyqh/ccov 
Full privdec code coverage
 2025-04-15 12:33:16 -07:00
Hamza Jamal
8f2be97dd4 sync with changes to riscv-arch-test trap handler 2025-04-15 09:08:29 -07:00
Corey Hickson
1a3bcc69a6 Full privdec code coverage 2025-04-15 02:47:53 -07:00
David Harris
81951d59ab Typo fix 2025-04-14 15:51:15 -07:00
David Harris
64ff263681 pmpadrdecs.S hits ifu and lsu pmp coverage 2025-04-13 07:16:39 -07:00
David Harris
93ee64d14a Fixed comments in periph tests 2025-04-13 04:13:13 -07:00
David Harris
3101d27d95 Fixed Issue #1321 about wally32periph failing on rv32imc; removed SEIP tests from WALLY-periph-01 and put them in WALY-periph-s 2025-04-12 20:32:51 -07:00
David Harris
556f965757 Removed unused delegation 2025-04-12 20:25:25 -07:00
David Harris
81a848246a Converting illegal instruction from 00000000 to FFFFFFFF; the zeros is a compressed instruction, and is messing with the trap handler. 2025-04-12 18:16:41 -07:00
David Harris
080011dab6 Partial immu pmp coverage 2025-04-11 07:23:37 -07:00
Jordan Carlin
336f325307
Remove a few more quad related files 2025-04-06 07:33:40 -07:00
Jordan Carlin
1416139a7c
Remove custom versions of riscv-isac and riscv-ctg 2025-04-05 12:51:05 -07:00
David Harris
25dbebb75c Added flush instructions to exercise CacheWays ClearValid 2025-04-03 13:01:17 -07:00
Jordan Carlin
1c94928a47
Fix breker makefile 2025-03-29 18:29:04 -07:00
Jordan Carlin
af1d3d4dd7
Breker optimizations 2025-03-28 13:39:17 -07:00
Jordan Carlin
3ff22586cb
Actually fix breker customer.yaml file this time 2025-03-21 01:42:03 -07:00
Jordan Carlin
300fcd669f
Fix Breker make clean 2025-03-20 20:30:59 -07:00
Jordan Carlin
bdcd0e85dd
Clean up individual Breker constraint files 2025-03-20 20:30:47 -07:00
David Harris
d7a026e736 Fixed more MMU tests with bad non-leaf A/D PTE bits 2025-02-27 03:37:23 -08:00
David Harris
28f5b5b6ed Fixed more MMU tests 2025-02-27 03:28:18 -08:00
David Harris
0bbc14d8f7 More test fixes 2025-02-26 16:02:12 -08:00
David Harris
057a30521b Fixed more coverage tests with bad non-leaf PTEs containing A or D bits 2025-02-26 15:51:27 -08:00
David Harris
2d000a3957 Modified eub.S tests to turn off A/D bits in non-leaf PTEs to avoid throwing page fault exceptions, which are not correctly detected 2025-02-26 09:32:10 -08:00
Jordan Carlin
caa4d27a99
Allow generating multiple Breker tests per constraint file 2025-02-23 01:00:18 -08:00
Jordan Carlin
4595e2cfb6
Enable ruff import sorting 2025-02-15 15:44:24 -08:00
Jordan Carlin
3c74f37e59
Update name of sail executables 2025-01-30 09:48:05 -08:00
Jordan Carlin
46ef44de5d
Update breker and enable interrupts 2025-01-30 00:58:53 -08:00
Jordan Carlin
bbc815d289
Merge branch 'main' of https://github.com/openhwgroup/cvw into python_updates 2025-01-23 00:39:05 -08:00
Jordan Carlin
e0c4eee86c
Update riscv-arch-test and enable remaining Zcf and Zcd tests 2025-01-17 10:32:28 -08:00
Jordan Carlin
9f0aebbcea
Merge branch 'main' of https://github.com/openhwgroup/cvw into python_updates 2025-01-03 14:28:27 -08:00
Jordan Carlin
f890cc9fd6
Enable riscv-arch-test vm sv32 tests in regression 2024-12-30 12:37:27 -08:00