The Ubuntu xenial-provided versions of setuptools and pip don't parse
all metadata present in Python packages, especially not the "minimum
required Python version" bit. More and more packages are using this
information to limit Python 3.5-support to older versions of their
packages. In this case, the problem was caused by the "zipp" package,
which is a very remote dependency of fusesoc.
Fixes#597
Update code from upstream repository https://github.com/google/riscv-
dv to revision 6e2bc2e01fb20799c9eff29a26852eb1917b977a
* fix a missed syntax error in pmp_cfg (Udi Jonnalagadda)
Signed-off-by: Udi <udij@google.com>
This commit modifies the `mip` CSR to not depend on the `mie` CSR. While
the values of both these CSRs are combined to decide whether an
interrupt shall be handled, the RISC-V spec does not state that the
content of of `mip` should depend on `mie`. This commit better aligns
Ibex with other open-source RISC-V cores.
This resolveslowRISC/ibex#567 reported by @pfmooney.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
In `VerilatorMemUtil::WriteElfToMem`, the verilator memory is written
with the ELF segment data, 4 bytes at a time . If the segment size isn't
a multiple of 4 (e.g. when using the RISC-V C extension) the last word
wouldn't be written. This patch rounds the size up to a multiple of 4,
solving that issue.
For some reason the part number between the Arty A7-35T and the Arty
A7-100T differs by 1 letter (TICSG vs TCSG). This patch fixes the part
number for the Arty A7-100T to remove the "i".
Signed-off-by: Stephano Cetola <scetola@linuxfoundation.org>
multdiv_sel signals the mult/div operand should be selected for the ALU
inputs. Previously the mult_en/div_en signals were used but these factor
in whether the instruction is actually happening which is not relevant
for the mux select. The dedicated select signal gives better timing.
Adds a second set of instruction flops that are used to determine ALU
operation and operand selection. This reduces fanout from the
instruction flops and so helps timing.
Riviera do not support parameters of dynamic/associate/queue array types.
The SV standard does not say explicitly that such code is legal.
IMHO this code is at least controversial as dynamic nature of such array
types are against static nature of parameters. It would be better to change
this "implemented_csr" from parameter to const.
This commit adds a separate memory ports for instruction and data
fetches to the Simple System example.
* Add Dual-Port RAM with 1 cycle read/write delay, 32 bit words.
* Introduce parametric signal width definitions for bus implementation
to work with a single host / device.
* Modify Simple System top module to instantiate the new dual-port RAM.
prim_assert.sv is a file containing assertion macros (defines).
Previously, prim_assert.sv was compiled as normal SystemVerilog file.
This made the defines available for the whole compilation unit as soon
as they were defined. Since all cores using prim_assert depended (in
fusesoc) on the lowrisc:prim:assert core, prim_assert was always
compiled first, and the defines were visible in subsequent files.
All of that is only true if all files end up in one comilation unit. The
SV standard states that what makes up a compilation unit is
tool-defined, but also states that typically, passing multiple files (or
a file list/.f file) to a single tool invocation means that all files
end up in one compilation unit; if the tool is called multiple times,
then the files end up in separate compilation units.
Edalize (the fusesoc backend) doesn't guarantee either behavior, and so
it happens that for Vivado, Verilator, Cadence and Synopsys simulators,
all files are compiled into a single compilation unit. But for Riviera,
each file is a separate compilation unit.
To avoid relying on the definition of compilation units, and to do the
generally right thing (TM), this commit changes the code to always
include the prim_assert.sv file when it is used in a source file.
Include guards are introduced in the prim_assert.sv file to avoid
defining things twice.
Two unused bits of device_err were only assigned in an initial block,
and it not in Verilator. They should have been tied off always to avoid
mixed blocking/nonblocking assignments to the same signal.
Update code from upstream repository https://github.com/google/riscv-
dv to revision a655f34eb5058da442b38ca010b0d008291c11b5
* Support running C test (google/riscv-dv#453) (Hai Hoang Dang)
* run.py: Do not compare csv file when specified -debug switch
(google/riscv-dv#451) (Hai Hoang Dang)
* adjust location of nested interrupt mstatus.mie enable
(google/riscv-dv#444) (udinator)
* Implement storing the commands that would be executed as a script
(google/riscv-dv#450) (Hai Hoang Dang)
* Move document from README to docs, add HTML preview for the new doc
(google/riscv-dv#448) (taoliug)
* Use single HTML format (google/riscv-dv#447) (taoliug)
* Update HTML document (google/riscv-dv#446) (taoliug)
* Add framework for custom extensions (google/riscv-dv#442) (taoliug)
Signed-off-by: Udi <udij@google.com>
Adds an 'uprate' clock period which is subtracted off the desired period
and given to ABC as the target clock period. This gives better overal
timing results with minimal area impact.
This commit adds a register file designed to be synthesized into FPGA
synchronous-write / asynchronous-read design elements.
For the artya7-100 example, the register file is implemented by 12
RAM32M primitives, conserving approximately 600 Logic LUTs and 1000
flip-flops at the expense of 48 LUTRAMs.
Signed-off-by: ganoam <gnoam@live.com>
Adds significant functionality to synthesis flow. Timing reports are
generated using OpenSTA and an area report is generated. Flow supports
open Nangate45 library from OpenROAD.
Refactors performance counters so only flops that are required from the
given parameters are explicitly elaborated without relying on
optimization to remove unused flops.
Fixes#473
This commit adds the performance monitor counters to the CS register
testbench. Mismatches in `mcycle(h)` are currently being ignored as the
cycle counter is expected to increment with every clock cycle (unless
deactivated).
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
