2195 commits

Author	SHA1	Message	Date
stnolting	b37c0646d7	minor updates	2020-07-12 22:40:33 +02:00
stnolting	a1aeb68464	added function to read system time (MTIME) via time[h] CSRs	2020-07-12 22:40:00 +02:00
stnolting	273efb9159	typo fix	2020-07-11 14:01:46 +02:00
stnolting	b3655e5afb	added [m]instret[h] and [m]cycle[h] access functions; make mtime read access roll-over safe	2020-07-11 13:07:30 +02:00
stnolting	16fd74de3f	using only instret[h] and cycle[h] for performance evaluation	2020-07-11 13:06:52 +02:00
stnolting	48ae50154a	added further tests	2020-07-10 19:50:33 +02:00
stnolting	1504d16b28	updates	2020-07-10 19:13:37 +02:00
stnolting	d2799f7e2e	updated bootloader	2020-07-09 16:52:43 +02:00
stnolting	aada5202c4	MTIME.time is now r/w (again); MTIME regs only allow full-word writes (to reduce hardware footprint)	2020-07-09 15:53:55 +02:00
stnolting	227516009b	misa CSR is read-only! mtval and mcause CSRs can now also be written by user; fixed error in bus unit - controller can now force bus unit reset and bus transaction termination	2020-07-09 14:21:13 +02:00
stnolting	662a3ce7d2	new default bootloader spi flash boot address is 0x0080_0000	2020-07-09 14:14:28 +02:00
stnolting	2ff653f600	cpu test now also prints project credits	2020-07-08 16:16:51 +02:00
stnolting	dfdb1544ed	added function to print project credits	2020-07-08 16:15:52 +02:00
stnolting	a3aaca62cc	text re-formatting	2020-07-07 22:22:10 +02:00
stnolting	c2edb1c885	fix in auto boot timeout output	2020-07-07 20:39:35 +02:00
stnolting	e643751244	added function for enabling/disabling CPU extensions (experimental!); optimized some functions to be always inlined	2020-07-07 19:14:00 +02:00
stnolting	d4e18558ac	added simple fence/fence.i test	2020-07-06 21:46:10 +02:00
stnolting	783dd11467	minor edits	2020-07-06 19:32:51 +02:00
stnolting	d38509fc92	removed mtinst CSR since it is not ratified by the official RISC-V specs yet	2020-07-06 19:32:20 +02:00
stnolting	a3cb008f8a	bug fixes	2020-07-05 23:14:46 +02:00
stnolting	940a5d80ba	added misa csr bits	2020-07-05 22:31:06 +02:00
stnolting	fa01809f60	updates due to new rte functions	2020-07-05 22:24:26 +02:00
stnolting	b31a77ecad	updated neorv32 rte	2020-07-05 22:24:08 +02:00
stnolting	fd16f64704	using csr pseudo-instruction for easier csr access	2020-07-05 22:22:59 +02:00
stnolting	75d71a036c	updated makefiles	2020-07-05 22:22:21 +02:00
stnolting	b66dd3fefd	added new generic to core sw library	2020-07-02 20:59:05 +02:00
stnolting	d7cff7622a	removed hw_analysis and exception_test projects; they are replaced by the cpu_test project	2020-07-02 20:55:00 +02:00
stnolting	dbf1d47b01	added simple xilinx vivado simulator waveform configuration file	2020-07-02 20:54:17 +02:00
stnolting	b0d72b8e37	added 'show hardware config' function to RTE; removed mscratch as return address buffer in crt0.S	2020-07-02 20:49:43 +02:00
stnolting	4b8d109388	bootloader now also shows mhartid	2020-07-02 20:48:08 +02:00
stnolting	a220448f82	minor edits	2020-07-01 21:44:51 +02:00
stnolting	e43f6f0654	minor edits	2020-06-28 22:16:18 +02:00
stnolting	b781c9d4f5	fixed bootloader bug introduced with last commit	2020-06-27 14:07:47 +02:00
stnolting	480ad78a84	MTIME.time register is now read-only	2020-06-27 13:53:29 +02:00
stnolting	6954df489d	updated bootloader	2020-06-27 13:52:20 +02:00
stnolting	ba991f4b09	minor edits	2020-06-26 23:56:01 +02:00
stnolting	def3cb5ee8	minor edits and updates	2020-06-25 20:16:17 +02:00
stnolting	ea0acbe2c7	added DEVNULL io device for testing and faster simulation console output	2020-06-25 20:15:37 +02:00
stnolting	ead0be3645	minor edits	2020-06-24 17:12:45 +02:00
stnolting	0da6665126	added example program for showing hardware configuration	2020-06-24 11:30:07 +02:00
stnolting	ea2948cdf9	modified travis CI test scripts	2020-06-23 22:43:59 +02:00
stnolting	7166dc9762	minor edits	2020-06-23 20:52:09 +02:00
stnolting	417479a18b	added exceptions/interrupts test program	2020-06-23 19:38:35 +02:00
stnolting	5a80bb9a99	minor edits	2020-06-23 17:55:38 +02:00
stnolting	bee421876a	initial commit	2020-06-23 17:43:03 +02:00