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470 commits 8 branches 8 tags 17 MiB
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57 commits

Author SHA1 Message Date
Olof Kindgren
2bcf4104d0 Add debug module 2024-10-13 22:24:00 +02:00
Olof Kindgren
0cf26fe4f9 Prepare for release 2024-07-06 16:54:53 +02:00
Olof Kindgren
783e92b576 Add missing descriptions to core description files 2024-06-16 09:45:26 +02:00
Olof Kindgren
109acd0a53 Prepare for release 2022-12-25 22:04:52 +01:00
Olof Kindgren
cb4276e8b2 Prepare for release 2022-07-26 01:19:28 +02:00
Abd
2655861447 Compressed Extension for SERV 2022-06-01 13:38:24 +02:00
Olof Kindgren
d910becd7f Move dbus_dat/rs2/shamt storage to bufreg2 2022-01-02 22:10:33 +01:00
Klas Nordmark
52d0bf0938 Added openlane target and params.tcl with suitable openlane parameters for SERV 2021-08-30 22:13:42 +02:00
Zeeshan Rafique
6e802cb9bc M-extension support for SERV 
* modified serv(ant) for MDU
* added dependency for mdu
* M-extension for SERV
* Updated README for running RV32IM compliance tests
* waive some lint warnings related to mdu
* added mdu param for arty_a7_35t
 2021-08-20 23:45:19 +02:00
Olof Kindgren
8e073546b8 Prepare for release 2021-08-09 23:12:18 +02:00
Olof Kindgren
c2cdd44f73 Expose and document PRE_REGISTER 2021-06-05 22:56:37 +02:00
Olof Kindgren
a5c1c8ddc4 Kill off serv_params.vh 2021-04-26 17:04:18 +02:00
Stefan Wallentowitz
cfb779d3d6 CI Lint with librecores github action linter 
Add the librecores linter, that also does proper annotation to the
source code.
 2021-04-18 23:02:04 +02:00
Olof Kindgren
0519ae4a52 Add verilator waiver file 2021-04-18 23:01:26 +02:00
Olof Kindgren
308612fd9e Expose WITH_CSR and RESET_STRATEGY in core file 2021-01-26 20:59:49 +01:00
Olof Kindgren
5e4181d204 Optimize shift operations 2021-01-18 22:46:51 +01:00
Olof Kindgren
a614e427b8 Move immediate decoder to separate module 2020-08-13 23:37:11 +02:00
Olof Kindgren
acbedbe9c4 Prepare for release 2020-05-26 22:52:09 +02:00
Olof Kindgren
707f63ae8c Rename ser_shift to serv_shift for consistency 2020-05-26 22:48:40 +02:00
Olof Kindgren
9606e3503d Inline shift_reg 2020-05-26 22:43:23 +02:00
Olof Kindgren
4f902829a3 Bump core version 2020-04-19 23:06:54 +02:00
Olof Kindgren
eff17d2f7c Prepare for release 2020-03-04 22:34:46 +01:00
Olof Kindgren
ea1936710e Inline ser_lt 2020-02-19 13:15:18 +01:00
Olof Kindgren
afb7e641dd Inline adders 2020-02-19 11:00:55 +01:00
Olof Kindgren
31c138e4a1 Create RAM and RF IF with configurable widths 2019-12-05 22:35:53 +01:00
Olof Kindgren
68d8af71f2 Use serv_rf_top in default and lint targets 2019-12-05 22:35:14 +01:00
Olof Kindgren
8b82c85fb6 Create toplevel without RF 2019-11-20 18:26:04 +01:00
Olof Kindgren
04037c4354 Split out RF to separate module 2019-11-20 18:26:04 +01:00
Olof Kindgren
9575eb4fef Separate decode and state 2019-09-15 23:25:10 +02:00
Olof Kindgren
f754fffdac Make default target runnable 2019-07-29 08:41:03 +02:00
Olof Kindgren
fe9d2677ba Add SERV_CLEAR_RAM parameter 2019-06-24 13:18:34 +02:00
Olof Kindgren
cf7e516526 Refactor to separate serv and servant 2019-06-24 13:18:34 +02:00
Olof Kindgren
42ac1e5e4d Store CSR in RF RAM 
Since FPGA uses fixed-size RAM, it's better in most cases to store
the CSR in unused memory positions in that RAM.

Since the decoding is made more complex, the old register file
implementation is kept around since that is more efficient when we
don't want CSR and potentially when the FPGA support hardware
shift registers.
 2019-06-07 19:39:18 +02:00
Olof Kindgren
bba836ad8c Fix width mismatches to make code verilator clean 2019-03-25 20:57:13 +01:00
Olof Kindgren
6e91409990 Optimize alu eq check 2019-03-20 08:35:43 +01:00
Olof Kindgren
fe33d6abdc Move dbus address handling to global bufreg 2019-01-15 08:00:32 +01:00
Olof Kindgren
1d04ed9c50 Fix errors in core file 2018-12-16 08:48:48 +01:00
Olof Kindgren
836a013462 Fix clock generation 2018-12-06 22:12:03 +01:00
Olof Kindgren
fc82862e96 Add icepll generator and run tinyfpga BX at 32MHz 2018-12-03 12:26:17 +01:00
Olof Kindgren
25791b10c2 Add memsize param to FPGA targets 2018-11-26 23:13:50 +01:00
Olof Kindgren
ec8252ea0a Add memsize parameter 2018-11-26 17:54:10 +01:00
Olof Kindgren
12039dec0e Add support for setting memory contents during synthesis 2018-11-26 09:49:08 +01:00
Olof Kindgren
e1f5bcc4f3 Rewrite register file 2018-11-26 00:09:52 +01:00
Olof Kindgren
f2e1e4a52b Add support for IceBreaker board 2018-11-22 13:03:23 +01:00
Olof Kindgren
47b2db20c3 Remove missing file from .core 2018-11-21 13:33:54 +01:00
Olof Kindgren
079d973969 Cleanup 2018-11-21 13:22:55 +01:00
Olof Kindgren
9df2a0060b Use custom interconnect. Runs on hw 2018-11-21 13:15:33 +01:00
Olof Kindgren
6e034361d4 Add UART decoder 2018-11-19 09:42:42 +01:00
Olof Kindgren
ff63519607 Temporary hack to blink LED on tinyfpga BX 2018-11-18 21:42:42 +01:00
Olof Kindgren
7666ac4092 synthesized netlist works 2018-11-18 13:05:38 +01:00