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Author	SHA1	Message	Date
Zbigniew Chamski	48ef515ba0	[Spike Yaml] Integrate Spike Yaml support. (#2304)	2024-07-11 08:37:37 +02:00
Côme	2dcb7417b4	make cv32a65x superscalar (#2348)	2024-07-10 23:33:49 +02:00
Asmaa Kassimi	214444cc93	csr_regfile lint error fix (#2346)	2024-07-10 13:13:26 +02:00
Jalali	dc9dc150e7	Increase supported PMP entries in UVM testbench (#2344)	2024-07-10 11:54:29 +02:00
JeanRochCoulon	58d490b461	Update PMP entry number from 16 to 64 (#2343)	2024-07-10 09:54:16 +00:00
Asmaa Kassimi	d9a7fdb836	condition branch_unit and alu (#2342)	2024-07-10 11:02:18 +02:00
LQUA	f44655809f	Add CV64A6_MMU core in user manual (#2324)	2024-07-09 16:49:31 +02:00
valentinThomazic	c50012ac76	Remove duplicate and out of date infos on verif readme (#2338)	2024-07-09 16:48:37 +02:00
Moritz Schneider	b6a3aa1b03	Fix non-standard usage of SystemVerilog (#2336) ... Strings cannot be initially assigned to an integer without a cast.	2024-07-09 10:39:52 +02:00
dependabot[bot]	7c351b3c8e	Bump verif/core-v-verif from 1173e7e to 2d9f96e (#2337)	2024-07-09 07:24:09 +02:00
Isaar Ahmad	0c58e39987	Update README.md : Updated gcc-toolchain-builder path (#2332)	2024-07-06 18:54:53 +02:00
Côme	37d93a3758	superscalar: do not issue CSR with another instruction (#2329)	2024-07-05 23:49:44 +02:00
André Sintzoff	51114ee0a1	machine.adoc: add missing table (#2331) ... For CVA6, add table: Encoding of A field in PMP configuration registers	2024-07-05 23:49:20 +02:00
Moritz Schneider	6044454a07	Fix index calculation for PMPCFG CSR write logic (#2330)	2024-07-05 22:56:27 +02:00
Asmaa Kassimi	67dba2cad3	condition csr_regfile.sv (#2310)	2024-07-05 14:14:01 +02:00
Côme	4df49a6b0f	superscalar: make SuperscalarEn a CVA6Cfg attribute (#2322)	2024-07-05 14:09:48 +02:00
valentinThomazic	051a2f94ff	Retry FPGA boot in CI when failed (#2325)	2024-07-05 12:06:42 +02:00
André Sintzoff	0bd8b8693a	update riscv-isa-manual to riscv-isa-release-ebf2e3a0b-2024-07-03 (#2323) ... since last riscv-isa-manual update (CVA6 commit 105d3601b): - minor documentation changes - use of docs-resources submodule inside riscv-isa-manual - requires asciidoctor-lists	2024-07-05 12:06:16 +02:00
Jalali	2616d5e649	add UVM interrupt agent (#2309)	2024-07-05 11:54:34 +02:00
Guillaume Chauvon	9900d5fd19	Fix benchmark.sh with correct GCC options and order (#2313)	2024-07-05 11:52:27 +02:00
Moritz Schneider	246961b3c3	Increase max num PMPs to 64 (#2279)	2024-07-04 14:09:37 +02:00
Mathieu Gouttenoire	d98ac1490a	New toolchain builder script for GCC and LLVM (#2320) ... * Move build-toolchain.sh * New toolchain builder script for GCC and LLVM	2024-07-04 09:46:41 +02:00
LQUA	66caecdfe6	Add RISCV documentation for cv64a6_mmu (#2315)	2024-07-03 17:24:07 +02:00
Jalali	702fedf23f	Fix issue #2479 #2468 (#2318)	2024-07-03 17:14:15 +02:00
Asmaa Kassimi	ace1643e91	Add lambda function to sort lint summary according to severity (#2316)	2024-07-03 16:46:30 +02:00
Jalali	f18bac51b3	Bump CVV to fix issue 2484 (#2302)	2024-07-02 17:41:23 +02:00
Jalali	9ebe42f033	Add illegal instruction to cover corner case in decoder (#2307)	2024-07-02 17:40:45 +02:00
Asmaa Kassimi	3874c41320	fix lint errors in csr_regfile.sv (#2306)	2024-07-02 15:36:04 +02:00
dependabot[bot]	0721ebb609	Bump verif/core-v-verif from 0e97e74 to 4531071 (#2305)	2024-07-02 08:23:22 +02:00
Côme	636e6aff47	superscalar add second ALU (#2303)	2024-06-30 18:24:11 +02:00
Zbigniew Chamski	aa5d7f8217	Bump CVV to use improved scoreboard reporting in tandem simulations. (#2301)	2024-06-28 15:28:07 +02:00
Côme	ce1e889716	update expected area (#2299)	2024-06-28 15:02:58 +02:00
Guillaume Chauvon	ced13a56b1	Fix typo on Bitmanip comment (#2300)	2024-06-28 15:01:50 +02:00
Jalali	33ab2efa83	Makefile : passing the tandem_enable value into UVM testbench (#2287)	2024-06-26 23:02:46 +02:00
xiaoweish	88f13c5874	Update uvml_mem use for core-v-verif's PR: 2480/2481/2482 (#2295)	2024-06-26 23:00:57 +02:00
xiaoweish	398778a1ba	Add vcs -full64 option back (#2294)	2024-06-26 22:58:55 +02:00
MarioOpenHWGroup	3f62e343fb	CI: Hash all the core-v-verif folder (#2296)	2024-06-26 20:51:58 +02:00
JeanRochCoulon	21383ce16d	Fix mstatus.mpp in relation to the possible legal values (#2285)	2024-06-21 17:27:48 +02:00
AbdessamiiOukalrazqou	ee0847e30a	[gen_from_riscv_config] add custom-gen.yaml support / fix hyperlinks in csr design doc / improve readme/fix csr_updater.yaml (#2286)	2024-06-21 17:19:42 +02:00
Moritz Schneider	fe1a19fca7	Fix WARL behavior of MPP (#2283) ... Related to #2274	2024-06-21 14:38:57 +02:00
André Sintzoff	21733e55d7	decoder.sv: add checks for some B instructions (fix #2276) (#2282)	2024-06-21 10:54:10 +02:00
Côme	96ae8ed223	superscalar: allow speculative instructions (#2278)	2024-06-20 15:55:56 +02:00
Michael Platzer	318be6dcde	Use correct fault type for VLSU overflow (#2273)	2024-06-19 21:31:00 +02:00
André Sintzoff	89568b0c10	doc: clarify mtval register description when not enabled (#2271)	2024-06-19 13:00:33 +02:00
Zbigniew Chamski	17ea49439f	[riscv-config] Update riscv-config tool, CV32A65X specs and the rendering of CSRs. (#2270)	2024-06-19 12:08:15 +02:00
Gregor Haas	c92245b20b	Implement simple uart-based updater for the bootrom (#2267)	2024-06-19 11:24:01 +02:00
Cesar Fuguet	9df64701bd	Update submodule core/cache_subsystem/hpdcache (#2265)	2024-06-18 11:54:35 +02:00
MarioOpenHWGroup	c78ede91f9	Bump CVV 2465 and adapt cva6pkg (#2263)	2024-06-17 16:49:10 +02:00
xiaoweish	c93587b1f9	Update UART submodule to version 0.2.1 and Use SV UART in vcs-testharness (#2196)	2024-06-17 09:24:18 +02:00
AngelaGonzalezMarino	db088159eb	Mmu design document (#2117)	2024-06-17 09:23:44 +02:00