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Author	SHA1	Message	Date
AbdessamiiOukalrazqou	e0da6e3569	Fix access issues for reserved fields (#2187)	2024-06-03 15:54:10 +02:00
AEzzejjari	1c828c0a16	Connect the new AXI agent with CVA6 (#2182)	2024-06-03 14:42:37 +02:00
André Sintzoff	ba6262a65c	add Unprivileged RISC-V ISA for CV32A65X doc (#2186)	2024-06-03 12:13:16 +02:00
Jalali	8e2393db99	Add the capability to add functional coverage results into the dashboard (#2183)	2024-06-03 11:47:22 +02:00
MarioOpenHWGroup	d89c5b6ba6	Disable misa we in rm (#2181)	2024-06-03 10:58:22 +02:00
AngelaGonzalezMarino	3e907d625f	fix tval in mmu (#2124)	2024-05-31 15:26:33 +02:00
André Sintzoff	227a3f4ff9	doc cv32a65x: update xPELP fields in mstatus (#2177)	2024-05-31 12:48:12 +02:00
Jalali	ae4392e958	CORE-DV : Merge all exception handlers in one to optimize time simulation (#2175)	2024-05-31 12:39:58 +02:00
Jalali	9ddebe25ae	HOTFIX : ignore instr_addr_misaliged exception only when also there's a trap (#2174)	2024-05-31 12:39:48 +02:00
Zbigniew Chamski	c30c20bc2b	[riscv-config] HOTFIX: Regenerate output files for CV32A65X. (#2176)	2024-05-31 12:39:10 +02:00
Cyprien Heusse	46e9d5a7fc	32 bits WB cache (#2170)	2024-05-30 18:47:39 +02:00
André Sintzoff	718c4e23b3	update riscv-isa-manual to riscv-isa-release-1bec7d3-2024-05-28 (#2169)	2024-05-30 17:54:30 +02:00
MarioOpenHWGroup	d714d833cb	Bump verif/core-v-verif from f7bda8e to NOTMERGED (#2044)	2024-05-30 15:57:58 +02:00
JeanRochCoulon	0da83492f6	Give information on how to clean-up Spike before build (#2164)	2024-05-30 13:40:51 +02:00
JeanRochCoulon	8630458370	Parametrization: Use CVA6Cfg.WtDcacheWbufDepth in place of DCACHE_WBUF_DEPTH (#2166)	2024-05-30 12:26:58 +02:00
Côme	93648e8cf7	Revert "Functional coverage report in CI (#2127)" (#2168) ... This reverts commit d4f984dbce.	2024-05-30 10:37:56 +02:00
Jalali	c50c4770f5	TRAPS VERIF : Add checking pc after a trap and remove unnecessary coverage (#2167)	2024-05-30 09:02:24 +02:00
Zbigniew Chamski	2534713373	[riscv-config] Fix issues in CV32A65X input spec and regenerate output. (#2165)	2024-05-29 17:35:47 +02:00
André Sintzoff	4df326e13c	utils.py: format and fix typos (#2163)	2024-05-29 09:37:46 +02:00
JeanRochCoulon	b6495684ba	Insert CSR generated from riscv-config (#2162)	2024-05-29 09:37:31 +02:00
AngelaGonzalezMarino	f8914b9237	Mmu user manual (#2118)	2024-05-28 17:45:22 +02:00
JeanRochCoulon	83191f4c3f	Change spike.yaml location (#2160)	2024-05-28 13:25:43 +02:00
xiaoweish	8cb7a8a4ed	fix gcc-14 compile error on: implicit-function-declaration, implicit-int (#2159)	2024-05-28 07:04:10 +02:00
dependabot[bot]	691c480aea	Bump core/cache_subsystem/hpdcache from 57c82d3 to 32407cb (#2157)	2024-05-27 23:06:50 +02:00
dependabot[bot]	987cbc06c3	Bump verif/core-v-verif from 4e6e860 to 399438e (#2158)	2024-05-27 23:06:20 +02:00
JeanRochCoulon	f0adb7680b	Update the specification following the last commits (RVF, SUPERSCALAR,...) (#2155)	2024-05-27 18:02:40 +02:00
AbdessamiiOukalrazqou	8fbfe3e57a	add gen from riscv config software (#2156)	2024-05-27 18:01:56 +02:00
Zbigniew Chamski	d1c6aab1f0	[UVM TB] Initialize information about DRAM address and size. (#2153)	2024-05-27 16:13:12 +02:00
AEzzejjari	f0deb6104c	axi Specification: Modify the AXI memory interface specification (#1960)	2024-05-27 11:52:27 +02:00
Cyprien Heusse	dd98076a85	tb_wb_dcache updated and adapted for 32-bits (#2151)	2024-05-27 10:13:29 +02:00
Asmaa Kassimi	6164ecbae2	Create Spyglass CI job and add Spyglass folder to cva6 repository (#2131)	2024-05-24 14:16:15 +02:00
slgth	9f4b2f7179	New target with MMU: cv64a6_mmu (#2149)	2024-05-24 13:39:00 +02:00
Jalali	7f31e76ac1	CSR REG PREDICTOR : Skip getting package on traps (#2130)	2024-05-23 18:13:44 +02:00
JeanRochCoulon	f4109564fd	Update PMA description (#2148)	2024-05-23 14:26:22 +02:00
AngelaGonzalezMarino	be14a84165	Add the condition for updating the tlb only after a miss is incurred (#2120)	2024-05-23 11:50:37 +02:00
AngelaGonzalezMarino	f8b07f09ab	Invalid pte reserved (#2123)	2024-05-23 11:50:09 +02:00
JeanRochCoulon	3d501bb485	Add SPP, SIE, SPIE, MXR and SUM description when S-mode is not implemented. (#2147)	2024-05-23 11:25:29 +02:00
xiaoweish	4e9c6ac9a3	Update testlist yaml with #2073 PR using yaml anchor/alias (#2146)	2024-05-23 11:25:04 +02:00
xiaoweish	115b464a2b	Two minor simulation flow enhancements (#2145)	2024-05-23 08:28:01 +02:00
Cyprien Heusse	e823d836f3	Fix bug when killing WB cache request (#2142)	2024-05-22 23:40:11 +02:00
Jalali	bdc7c975e2	Disable warnings in Code coverage Job (#2144)	2024-05-22 19:04:31 +02:00
JeanRochCoulon	73d3814fbd	Continue parametrization: as two localparams are not more used by UVM, remove them (#2141)	2024-05-22 18:13:28 +02:00
MarioOpenHWGroup	b48a2bb63d	[CSR] Fix bits when RVS and RVU not available (#2074)	2024-05-22 15:54:51 +02:00
Jalali	1c6da9b739	Fix issue #2027 (#2140)	2024-05-22 11:01:53 +02:00
Jalali	26e6a8de4e	HOTFIX: update HVP & CC report script to solve an error in CC JOb (#2139)	2024-05-21 21:32:08 +02:00
AEzzejjari	26d955d4d1	Set env_cfg directly from the CVA6 configuration. (#2138)	2024-05-21 12:32:24 +02:00
Jalali	e7f7b3d024	Fix issue #2027 Remove localparam (#2137)	2024-05-21 12:13:46 +02:00
Cesar Fuguet	f32f51777f	Add in Github's CI a 64-bit configuration of the CVA6 using the HPDcache and restore WB cache test (#2114)	2024-05-21 09:51:10 +02:00
Zbigniew Chamski	e6c3bac01e	[CI] Fix spike version checks on the CVA6 (#2135)	2024-05-21 08:55:25 +02:00
Jalali	137bd455a7	Functional coverage : Fix config values in sanity check (#2134)	2024-05-21 08:54:01 +02:00