André Sintzoff
67a6ae966c
update riscv-isa-manual to riscv-isa-release-2c07aa2-2024-10-18 ( #2560 )
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Since last riscv-isa-manual update (CVA6 commit 3059b1cb2
2024-10-22 14:44:02 +02:00
Zbigniew Chamski
cff48e4c75
Add tandem verification documentation ( #2553 )
bender-up-to-date / bender-up-to-date (push) Waiting to run
ci / build-riscv-tests (push) Waiting to run
ci / execute-riscv64-tests (push) Blocked by required conditions
ci / execute-riscv32-tests (push) Blocked by required conditions
2024-10-17 11:38:54 +02:00
André Sintzoff
48480c72d0
tristan doc: move files to sub-directory
2024-10-17 08:56:21 +02:00
André Sintzoff
a0f9deabff
tristan: add 2024 work
2024-10-17 08:56:21 +02:00
André Sintzoff
be4a6ee364
tristan_verification_specifications.adoc: 2023 version
2024-10-17 08:56:21 +02:00
André Sintzoff
5131fb030c
doc PMP: rephrase PMP configuration description ( #2540 )
2024-10-11 09:12:22 +02:00
EasyIP2023
37b58243fa
docs: expand wy-nav-content width to edge of screen ( #2452 )
2024-08-22 18:10:19 +02:00
André Sintzoff
3059b1cb25
update riscv-isa-manual to riscv-isa-release-5ddbdd678-2024-08-01 ( #2434 )
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since last riscv-isa-manual update (CVA6 commit 0bd8b8693
2024-08-07 11:52:07 +02:00
slgth
6a649d6515
docs: more fixes ( #2412 )
2024-07-26 23:49:41 +02:00
slgth
2249202769
docs: multiple fixes ( #2409 )
2024-07-26 15:27:42 +02:00
slgth
e9648eaf8c
Design documentation: AsciiDoc conversion ( #2399 )
2024-07-25 17:18:27 +02:00
slgth
3deb95af21
cv64a6_mmu: add RISC-V ISA documentation to main page ( #2393 )
2024-07-25 08:37:27 +02:00
JeanRochCoulon
8d413b7c54
doc PMA: cv32a65x is always idempotent and without caches ( #2377 )
2024-07-22 11:15:06 +00:00
André Sintzoff
8c70976759
docs: use correct commit for riscv-isa-manual submodule ( #2368 )
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fix after 8fa590b5c
2024-07-15 12:42:07 +00:00
Jérôme Quévremont
c4b4216981
Update cva6_requirements_specification.rst ( #2364 )
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Specify CV-X-IF version supported: 1.0.0.
Mention of B extension (with includes the Zb* extensions, already in the specification).
Make FENCE.T as a "should" instead of "shall" as we do not have plans to integrate it yet.
2024-07-12 18:14:26 +02:00
Côme
0cbd894a7a
update port and config docs ( #2363 )
2024-07-12 17:00:36 +02:00
jzthales
71653038d7
Doc lsu ( #2359 )
2024-07-12 16:49:02 +02:00
Guillaume Chauvon
8fa590b5c3
CVXIF 1.0.0 ( #2340 )
2024-07-12 10:53:18 +02:00
JeanRochCoulon
58d490b461
Update PMP entry number from 16 to 64 ( #2343 )
2024-07-10 09:54:16 +00:00
LQUA
f44655809f
Add CV64A6_MMU core in user manual ( #2324 )
2024-07-09 16:49:31 +02:00
André Sintzoff
51114ee0a1
machine.adoc: add missing table ( #2331 )
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For CVA6, add table:
Encoding of A field in PMP configuration registers
2024-07-05 23:49:20 +02:00
André Sintzoff
0bd8b8693a
update riscv-isa-manual to riscv-isa-release-ebf2e3a0b-2024-07-03 ( #2323 )
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since last riscv-isa-manual update (CVA6 commit 105d3601b
2024-07-05 12:06:16 +02:00
LQUA
66caecdfe6
Add RISCV documentation for cv64a6_mmu ( #2315 )
2024-07-03 17:24:07 +02:00
André Sintzoff
89568b0c10
doc: clarify mtval register description when not enabled ( #2271 )
2024-06-19 13:00:33 +02:00
AngelaGonzalezMarino
db088159eb
Mmu design document ( #2117 )
2024-06-17 09:23:44 +02:00
slgth
802066bfd3
docs: move riscv-isa-manual outside of cv32a65x documentation ( #2264 )
2024-06-16 23:20:41 +02:00
JeanRochCoulon
7e8e2c931f
Fix CSR chapter insertion and rename Design Doc names (remove "for cv32a65x") ( #2262 )
2024-06-14 15:39:22 +02:00
André Sintzoff
105d3601b6
update riscv-isa-manual to riscv-isa-release-c8c8075-2024-06-12 ( #2253 )
2024-06-13 16:45:04 +02:00
slgth
b1850a8cb7
docs: fix spec_builder.py ( #2249 )
2024-06-12 20:07:22 +02:00
André Sintzoff
361b17e7b0
cv32a65x doc: fix RISC-V unpriv pdf generation
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issue introduced in 718c4e23
2024-06-12 11:32:36 +02:00
André Sintzoff
d5b7cc77ff
cv32a65x doc: split unpriv and priv HTML pages
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Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2024-06-12 11:18:31 +02:00
slgth
f57a6c0106
Move CV32A65X documentation into its own chapter ( #2236 )
2024-06-11 18:01:25 +02:00
JeanRochCoulon
91871d97f3
Update functionality.rst ( #2235 )
2024-06-11 12:31:52 +02:00
JeanRochCoulon
9d02734bd1
Fix PMPCFG number (from 8 to 4, from which 2 are read-only zero) ( #2232 )
2024-06-11 11:15:27 +02:00
André Sintzoff
ba6262a65c
add Unprivileged RISC-V ISA for CV32A65X doc ( #2186 )
2024-06-03 12:13:16 +02:00
André Sintzoff
227a3f4ff9
doc cv32a65x: update xPELP fields in mstatus ( #2177 )
2024-05-31 12:48:12 +02:00
André Sintzoff
718c4e23b3
update riscv-isa-manual to riscv-isa-release-1bec7d3-2024-05-28 ( #2169 )
2024-05-30 17:54:30 +02:00
JeanRochCoulon
b6495684ba
Insert CSR generated from riscv-config ( #2162 )
2024-05-29 09:37:31 +02:00
AngelaGonzalezMarino
f8914b9237
Mmu user manual ( #2118 )
2024-05-28 17:45:22 +02:00
JeanRochCoulon
f0adb7680b
Update the specification following the last commits (RVF, SUPERSCALAR,...) ( #2155 )
2024-05-27 18:02:40 +02:00
AEzzejjari
f0deb6104c
axi Specification: Modify the AXI memory interface specification ( #1960 )
2024-05-27 11:52:27 +02:00
JeanRochCoulon
f4109564fd
Update PMA description ( #2148 )
2024-05-23 14:26:22 +02:00
JeanRochCoulon
3d501bb485
Add SPP, SIE, SPIE, MXR and SUM description when S-mode is not implemented. ( #2147 )
2024-05-23 11:25:29 +02:00
André Sintzoff
c52fd2b2c9
Provide RISC-V ISA priv in ReadTheDocs ( #2093 )
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* Provide RISC-V ISA for CV32A65X
* Reorder specifications in ReadTheDocs
2024-05-02 15:20:09 +02:00
JeanRochCoulon
f57efabd6b
doc priv: tailor machine.adoc for CV32A65X ( #2092 )
2024-05-02 10:28:23 +00:00
André Sintzoff
ecee022457
doc priv: tailor RISC-V privilege spec for CV32A65X ( #2078 )
2024-04-30 10:30:41 +02:00
JeanRochCoulon
e1d61182b7
Generate the cv32a65x riscv specification out of the box ( #2054 )
2024-04-22 15:34:21 +02:00
JeanRochCoulon
9a36bf2c3d
define riscv-isa-manual as submodule ( #2052 )
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* remove riscv-isa-manual vendor
* Define riscv-isa-manual as submodule
2024-04-17 12:45:43 +00:00
Côme
f886713754
User config generator becomes a Python tool to work with configs ( #2003 )
2024-04-04 15:56:29 +02:00
JeanRochCoulon
4423feb06a
Rename ZiCondExtEn and FPGA_EN parameters ( #1992 )
2024-04-02 15:37:58 +02:00
