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358 commits 16 branches 13 tags 288 MiB
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Author SHA1 Message Date
Florian Zaruba
fc6f669685 Prevent CSR instructions from forwarding 2017-06-03 16:57:25 +02:00
Florian Zaruba
f23f527006 Change ISA code 64 bit param 2017-06-03 16:22:04 +02:00
Florian Zaruba
618767d789 Make branch unit a standalone functional unit 2017-06-03 16:08:11 +02:00
Florian Zaruba
4d11e98b82 Beautify print instructions 2017-06-03 15:04:25 +02:00
Florian Zaruba
f57574e1eb First test not hanging anymore 2017-06-02 19:09:53 +02:00
Florian Zaruba
dad9c24d83 Re-implement forwarding 2017-06-02 19:00:26 +02:00
Florian Zaruba
d7771c83d7 Re-add assertions 2017-06-02 18:56:09 +02:00
Florian Zaruba
a4f2d965f0 New scoreboard implementation (simplified) 2017-06-02 18:55:25 +02:00
Florian Zaruba
a4ccd3c85d 🐛 Fix destination encoding for AUIPC 2017-06-02 17:53:59 +02:00
Florian Zaruba
80408364e3 🐛 Various bug fixes 2017-06-02 17:16:13 +02:00
Florian Zaruba
dbfbcd65c1 Re-trigger CI 2017-06-02 11:47:23 +02:00
Florian Zaruba
473aee92ab Fix issue #40 2017-06-02 11:42:42 +02:00
Florian Zaruba
72b842eaf8 Fix issue #39 2017-06-02 10:56:16 +02:00
Florian Zaruba
602116f2e7 Correctly implement interrupt stack 2017-06-01 18:11:46 +02:00
Florian Zaruba
7bb46a8556 [WIP] Implement return from exception 2017-06-01 16:55:15 +02:00
Florian Zaruba
8df9bbd84d Fix instruction tracer flush signals 2017-06-01 12:33:59 +02:00
Florian Zaruba
8390b2f26d 🐛 Various fixes in flush logic 2017-06-01 11:51:48 +02:00
Florian Zaruba
a2365104d3 [WIP] Implement ecall and ebreak instructions 2017-06-01 10:43:26 +02:00
Florian Zaruba
4d7b9a1b75 [WIP] Implement exception handling 2017-05-31 23:17:07 +02:00
Florian Zaruba
00b11efc6f Add features to instruction tracer 2017-05-30 20:18:13 +02:00
Florian Zaruba
da62924f81 Add decode, issue, flush and commit logic to tracer 2017-05-30 15:44:01 +02:00
Florian Zaruba
e29a923ca2 🐛 Couple of LSU related fixes 2017-05-30 12:28:23 +02:00
Florian Zaruba
a60ca39621 Add mock D$ implementation 2017-05-30 10:46:46 +02:00
Florian Zaruba
7d0ca57a9e 🎨 Update wave.do files 2017-05-30 10:20:13 +02:00
Florian Zaruba
0ef1bbd4ca Store queue scoreboard functional 2017-05-30 10:07:19 +02:00
Florian Zaruba
e99b6abab7 First (non-functional) store queue scoreboard impl 2017-05-29 20:51:36 +02:00
Florian Zaruba
4dd54df629 Re-add test target to Makefile 2017-05-29 19:34:12 +02:00
Florian Zaruba
3e387fcae3 First store queue driver implementation 2017-05-29 19:31:23 +02:00
Florian Zaruba
0c8587fd73 Add store queue sequence item 2017-05-29 19:13:20 +02:00
Florian Zaruba
d6526b2eb1 Instantiated dcache interface for store queue test 2017-05-29 19:09:14 +02:00
Florian Zaruba
db0ba0d6e1 Mock UVM store queue interface 2017-05-29 18:47:58 +02:00
Florian Zaruba
778d63355b Remove flush logic from arbiter, moved to units 2017-05-29 18:36:28 +02:00
Florian Zaruba
b2ad6f058e Implement monitor of dcache interface, test passing 2017-05-29 18:15:52 +02:00
Florian Zaruba
c1269588c4 Fix .gitlab-ci.yml 2017-05-29 16:46:19 +02:00
Florian Zaruba
f0b3476d98 Merge branch 'initial-dev' of iis-git.ee.ethz.ch:floce/ariane into initial-dev 2017-05-29 16:41:30 +02:00
Florian Zaruba
be9d35da29 📝 Slightly update LSU timing diagrams 2017-05-29 16:41:08 +02:00
Florian Zaruba
cb848654ff Implement response side 2017-05-29 16:25:27 +02:00
Florian Zaruba
b7303e41d2 Add request side of D$ interface 2017-05-29 16:15:11 +02:00
Florian Zaruba
5c7975ca05 🎨 Rename dcache arbiter wave file 2017-05-29 15:57:36 +02:00
Florian Zaruba
809f7f05b5 Revert deleted test folder 2017-05-29 15:53:10 +02:00
Florian Zaruba
aa50f69434 Adapt dcache arbiter testbench using new dcache if 2017-05-29 15:51:31 +02:00
Florian Zaruba
91a887da47 Add dcache interface as an agent 2017-05-29 14:46:32 +02:00
Florian Zaruba
f081730042 Merge branch 'initial-dev' of iis-git.ee.ethz.ch:floce/ariane into initial-dev 2017-05-29 14:32:19 +02:00
Florian Zaruba
b3b347a636 [WIP] Re-worked LSU dcache interface 
LSU should comply with the new LSU D$ interface as specified in the
previous commits. This is WIP, larger testbench changes will be
necessary. As the interface significantly diverged.
 2017-05-29 14:29:45 +02:00
Florian Zaruba
2d7d0a880e 📝 Updated LSU <-> D$ information 2017-05-29 11:09:59 +02:00
Florian Zaruba
b8284ddb80 📝 Add D$ interface documentation 2017-05-29 10:41:57 +02:00
Florian Zaruba
ba04445d27 🎨 Remove pre-fetch buffer, module was redundant 2017-05-27 19:12:13 +02:00
Florian Zaruba
35bdeb69d0 📝 Add further documentation and clean-up 2017-05-27 18:48:50 +02:00
Florian Zaruba
48587017ac Add regular behavioral RAM, no interface 2017-05-23 17:12:49 +02:00
Florian Zaruba
baf51e5354 Add core memory stub 2017-05-23 10:20:52 +02:00