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Author	SHA1	Message	Date
Fatima Saleem	4fb073f91c	[Docs] Adding Zicond in user and requirement specs (#1444)	2023-09-18 23:39:26 +02:00
Jalali	d8c3916ebc	Makefile : Fix env & tb path for the new repo (#1445)	2023-09-18 17:57:15 +02:00
Côme	7355fd7ce8	readme: use bash instead of sh (#1429)	2023-09-15 18:13:45 +02:00
Fatima Saleem	2ac676d931	Add Zicond Extension support in CVA6 (#1405)	2023-09-15 08:19:50 +02:00
Zbigniew Chamski	5c3e3d4545	Add GCC toolchain builder. Update README and .gitignore accordingly. (#1415)	2023-09-14 23:44:00 +02:00
Côme	5b37393a2e	fix verilator wavedump (#1395)	2023-09-13 22:36:19 +02:00
Côme	3e5ebdf4f4	Fix cleaning in coremark and dhrystone (#1396)	2023-09-13 22:35:19 +02:00
Florian Zaruba	91df62885f	Parametrize debug module (#1382)	2023-09-13 16:22:24 +02:00
Côme	3b90bcf4aa	Update CI readme after merging cva6 and core-v-verif (#1390)	2023-09-13 16:15:41 +02:00
Côme	1ea9ced9a9	Don't use submodules to merge reports (#1383)	2023-09-13 16:14:11 +02:00
JeanRochCoulon	c71690acaf	[HOT FIX] update expected_synth.yml (#1392)	2023-09-13 10:08:38 +02:00
JeanRochCoulon	74c8d2fc9c	Updating the Github task (#1391)	2023-09-12 23:30:38 +02:00
JeanRochCoulon	d6bb5deabf	HOT FIX, update expected_synth.yml ... Previous merge has reduced the gate count, this commit fixes it.	2023-09-12 23:26:59 +02:00
Fatima Saleem	a548c9dac8	Updating the Github task	2023-09-12 22:07:47 +05:00
JeanRochCoulon	de986ed17f	Hardwire the reserved bits of the PMPCFG CSR to 0 (#1368)	2023-09-11 18:22:59 +02:00
JeanRochCoulon	00f113b4a9	Bump verif/core-v-verif from d5e2c22 to 03ea736 (#1378)	2023-09-11 15:50:46 +02:00
JeanRochCoulon	2b8c7a0178	Remove Rename Block (#1359)	2023-09-11 15:40:33 +02:00
JeanRochCoulon	f7b79535df	add tools to gitignore (#1379)	2023-09-11 12:08:48 +02:00
dependabot[bot]	18076790d5	Bump verif/core-v-verif from d5e2c22 to 03ea736 ... Bumps [verif/core-v-verif](https://github.com/openhwgroup/core-v-verif) from `d5e2c22` to `03ea736`. - [Release notes](https://github.com/openhwgroup/core-v-verif/releases) - [Commits](d5e2c2206c...03ea736afe) --- updated-dependencies: - dependency-name: verif/core-v-verif dependency-type: direct:production ... Signed-off-by: dependabot[bot] <support@github.com>	2023-09-11 08:49:23 +00:00
JeanRochCoulon	a9be34a029	Add dependabot to update verif/core-v-verif (#1373) ... Dependabot is executed on Monday	2023-09-11 10:49:05 +02:00
Côme Allart	e7316aa331	add tools to gitignore	2023-09-08 17:10:29 +02:00
Fatima Saleem	2921f877ed	updated the gates count for embedded config	2023-09-07 21:44:40 +05:00
Fatima Saleem	2a249ad62d	removing the rename param from CI	2023-09-07 20:09:58 +05:00
Fatima Saleem	8febe20849	updating the REG_ADDR_SIZE	2023-09-07 20:02:48 +05:00
Fatima Saleem	23098693d9	removed rename parameter from the config files	2023-09-07 20:02:48 +05:00
Fatima Saleem	8355a70ade	removed rename block	2023-09-07 20:02:48 +05:00
Côme Allart	06ca8b82ed	add dependabot to update verif/core-v-verif	2023-09-07 15:53:42 +02:00
JeanRochCoulon	1c847c3e27	Merge core-v-verif and cva6 (#1351)	2023-09-07 15:38:32 +02:00
Moritz Schneider	4c663fc164	Hardwire the reserved bits of the PMPCFG CSR to 0 ... This realigns CVA6 with spike (#1346) Signed-off-by: Moritz Schneider <moritz.schneider@inf.ethz.ch>	2023-09-07 14:35:03 +02:00
Côme Allart	a828eb5069	fix GIT_STRATEGY	2023-09-07 14:03:58 +02:00
Jean-Roch Coulon	1dd9773c8c	Update README.md to give recommandations to setup environment and execute tests ... Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>	2023-09-07 11:38:34 +02:00
Côme Allart	10ea8240d2	fix CI	2023-09-07 11:38:34 +02:00
Côme Allart	aa03f6a307	add pipeline rules from cva6's previous CI	2023-09-07 11:38:34 +02:00
Côme Allart	eb0af8975f	move ci from cvv	2023-09-07 11:38:34 +02:00
Côme Allart	efc01b47e4	remove old ci	2023-09-07 11:38:34 +02:00
Jean-Roch Coulon	b13530ccbc	fix regress tests and makefiles ... Co-authored-by: Côme Allart <come.allart@thalesgroup.com>	2023-09-07 11:38:34 +02:00
Côme Allart	1386369b50	add core-v-verif as a git submodule	2023-09-07 11:38:31 +02:00
Côme Allart	437734ccd0	update verif/.gitignore	2023-09-07 10:12:03 +02:00
Côme Allart	437b3ec556	merge core-v-verif's cva6-related parts	2023-09-07 10:04:25 +02:00
Côme Allart	736be43a73	move files to a verif directory	2023-09-07 09:50:50 +02:00
Côme Allart	e1f313251e	remove non-CVA6-specific files	2023-09-07 09:50:49 +02:00
Mike Thompson	d5e2c2206c	Merge pull request #2168 from openhwgroup/cva6/dev ... Merging of cva6/dev to master	2023-09-06 13:20:30 -04:00
JeanRochCoulon	0da4dff148	Fix STD Cache AXI w_valid Propagation (#1360)	2023-09-06 09:25:42 +02:00
Domenic Wüthrich	03c14db797	[std_cache_subsystem] Fix AXI w_valid propagation when aw_ready is dependent on w_valid	2023-09-06 06:10:14 +00:00
JeanRochCoulon	885be3c1e4	Add Direct D$ Access to acc_dispatcher (#1361)	2023-09-05 22:04:28 +02:00
Mike Thompson	8dac926e4c	Merge pull request #2106 from ThalesSiliconSecurity/CSRTEST ... ISACOV : Add csr directed tests	2023-09-05 12:04:05 -04:00
Domenic Wüthrich	d45fda6179	[acc_dipsatcher] Add dcache request ports	2023-09-05 15:28:53 +00:00
Domenic Wüthrich	7092e4a81e	[cva6] Connect acc dipatcher d$ ports to cache subsystem	2023-09-05 15:28:51 +00:00
Domenic Wüthrich	570c52992f	[std_cache_subsystem] Add fourth dcache request port	2023-09-05 15:27:35 +00:00
Domenic Wüthrich	aad93781e5	[wt_cache] Add third read port	2023-09-05 15:27:00 +00:00