to have same behaviour on spike and on RTL with one core,
do not yield load reservation at the end of each block of
INTERLEAVE steps
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Adding Legal values to MTVEC and STVEC registers to fix#1060 and #1079 issues
* Updating MTVEC and STVEC description
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Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
* Clean-up README.md and top-level directory
This removes the duplicate `scripts` and `util` directories. Furthermore
the README is condensed by collapsing the citation and adding the
CITATION file to the repository.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
* Re-name icache req/rsp structs
The structs used to communicate with the icache have contained the
direction, which makes no sense for structs since they inherently don't
have any direction.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
---------
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
Each job needs less code in cva6.yml
It also fixes an issue in CVV pipelines, where the CVA6 hash in the
dashboard was not the one used in some jobs of the pipeline.
* [lsu] Add external store buffer pending stall signal
* [controller] Add external acc request pipeline flush signal
* [frontend] Do not increment commit pc on flush if commit stage is halted
* [acc_dispatcher] Add new store buffer stall and flush pipeline ctrl signals
* [acc_dispatcher] Add top module passable config type and parameter
* [cva6] Pass on missing CVA6Cfg parameter to acc_dispatcher
A parameter called --isa_extension has been added in cva6.py. Depending on the set of instruction the user want to use while compiling/executing a code (assembly/c/elf) the user can choose the extension to enable via this argument. i,m,a,f,d,c,g,v are not supposed to be specified here only z_, s_, or x_ extensions can be added via this argument. This argument is set to zicsr by default.
Ex: python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a60x --iss= --isa_extension=zicsr,zbb
In this example, the extension zicsr and zbb has been added to the isa initially associated to the target cv32a60x.
Implementation of a new argument isa_extension in cva6.py to switch to gcc 13.1.0.
This argument includes the specific extensions to add to the isa for compilation.
It takes zicsr by default (extension to enable csr instructions).
Bugs fixed on: dv-riscv-compliance and dv-riscv-tests (need of enabling zifencei also), smoke_test (use of one linker instead of two).
* add axi parameters to cfg
* Move axi_intf.sv from core to corev_apu
* Move ariane_axi_pkg.sv from core to corev_apu
* Merge axi and l15 into noc
* Fixes to build and run openpiton
---------
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jonathan Balkind <jbalkind@ucsb.edu>
