Côme
bd4b57cc64
Parametrization step 3 part 3 (last) ( #1940 )
2024-03-18 16:19:52 +01:00
Côme
4817575de9
Parametrization step 3 part 2 ( #1939 )
2024-03-18 12:06:55 +01:00
André Sintzoff
9a713c3b17
smoke-tests.sh: run first I-ADD-01 test for cv64a6_imafdc_sv39 ( #1934 )
2024-03-15 18:14:32 +01:00
Jalali
6851499b18
Add directed Tests for jump instructions ( #1933 )
2024-03-15 15:16:21 +00:00
valentinThomazic
fd12ee596c
Add smoke-tests and fpga logs on dashboard ( #1928 )
2024-03-14 14:43:56 +01:00
Rohan Arshid
c827c3b770
Zcmp extension support ( #1779 )
2024-03-13 11:37:49 +01:00
Côme
83d94bbb69
transform rvfi types into macros ( #1921 )
2024-03-12 17:34:27 +01:00
valentinThomazic
fde7e856e7
detect old versions of spike ( #1910 )
2024-03-08 23:54:05 +01:00
Jalali
bb2c6bd41f
Code coverage : Exclude unread module form CC (fix issue #1903 ) ( #1907 )
2024-03-08 18:35:01 +01:00
André Sintzoff
8c2bbb0527
cva6.py: fix typos in displayed messages ( #1906 )
2024-03-08 14:01:19 +01:00
valentinThomazic
a4fc0e9f99
Check tools version before simulation ( #1899 )
2024-03-07 16:34:10 +01:00
Côme
13dfa744d2
Parametrization step 1 ( #1896 )
2024-03-06 17:02:55 +01:00
Zbigniew Chamski
4fcdf4ea30
Generate separate per-target logs when simulating. ( #1870 )
2024-03-05 19:37:57 +01:00
Zbigniew Chamski
16bdcda07c
Improve environment setup. Fix Verilator installation process. ( #1864 )
...
* verif/sim/setup-env.sh: Double-quote variable values. Install Verilator
in 'tools/verilator' by default. Add SPIKE_PATH to PATH.
* verif/regress/install-verilator.sh: By default use per-version dirs to
build and install Verilator. Add and improve configuration messages.
2024-03-05 17:18:33 +01:00
Jalali
9f928e4c12
Exceptions : Add bins for Read-only CSRs ( #1885 )
2024-03-05 14:17:56 +01:00
Jalali
f5662fb49f
ISA DVPLAN : Add bit-manipilation instructions (Zb*) ( #1884 )
2024-03-05 14:17:20 +01:00
Jalali
ce0ab81630
Connect CSRs info from RVFI_CSR in the testbench & update simulation target ( #1879 )
2024-02-28 16:20:24 +01:00
Yannick Casamatta
1dec79464e
add csr in rvfi ( #1833 )
2024-02-24 00:10:23 +01:00
CoralieAllioux
68f952b44c
Update usage of riscv_instr_gen_tb_top as in other cores: adapt it in corev-dv to import cva6-dependent packages ( #1862 )
2024-02-23 23:28:10 +01:00
Jalali
514fb86738
Map AXI functional coverage to the HVP ( #1867 )
2024-02-23 18:04:58 +01:00
Jalali
9c4a3c37d6
Remove mcountinhibit from csr_test and UVM env ( #1863 )
2024-02-21 19:13:57 +01:00
dependabot[bot]
21deaa71dc
Bump verif/core-v-verif from 1955db4 to d466330 ( #1858 )
...
Bumps [verif/core-v-verif](https://github.com/openhwgroup/core-v-verif ) from `1955db4` to `d466330`.
- [Release notes](https://github.com/openhwgroup/core-v-verif/releases )
- [Commits](1955db4ef7...d46633081b
2024-02-21 11:17:10 +00:00
Jalali
5dd04829e3
ISA functional coverage : Add directed tests ( #1855 )
2024-02-21 09:31:54 +01:00
valentinThomazic
cedc21bb35
fixed Verilator detection by tests ( #1854 )
2024-02-20 19:30:40 +01:00
dependabot[bot]
a8c15ca366
Bump verif/core-v-verif from c7d2077 to 1955db4 ( #1852 )
2024-02-20 12:08:05 +01:00
CoralieAllioux
965fd914b2
Bugfix/riscv dv cyclic dependency ( #1853 )
2024-02-20 12:07:21 +01:00
AEzzejjari
5e80c104c9
AXI agent: Connect the the new AXI agent ( #1817 )
2024-02-18 23:31:44 +01:00
Jalali
3d7e417bce
Functional coverage : Add cross to illegal and exception coverage models ( #1839 )
2024-02-18 23:30:11 +01:00
Jalali
33a7a8207a
GEN_TESTS: Add --priv option to command generated tests ( #1831 )
2024-02-14 10:39:01 +01:00
MarioOpenHWGroup
c7f0eaf0d8
Bump verif/core-v-verif from fd68dfd to c7d2077 ( #1828 )
2024-02-13 14:20:21 +01:00
Zbigniew Chamski
d48c4b5b4e
Fix waveform generation using vcs-uvm. Add waveforms section to README. ( #1827 )
2024-02-13 12:08:18 +01:00
Jalali
3599839d2e
Functional coverage : Fix illegal cover_group sampling ( #1825 )
2024-02-12 16:16:38 +01:00
Jalali
5a9e1efd18
CVA6 HVP : MAP Illegal and exception covergroup into hvp ( #1819 )
2024-02-09 15:40:05 +01:00
Jalali
22e9173b84
Functional coverage : Create Unmapped instruction and exceptions coverage models ( #1818 )
2024-02-09 11:31:15 +01:00
dependabot[bot]
e46baf6944
Bump verif/core-v-verif from aa5fe84 to fd68dfd ( #1813 )
2024-02-07 10:54:46 +01:00
Jalali
877a07c368
CVA6 HVP : Map ZCB instructions & remove DRET instruction ( #1812 )
2024-02-06 23:38:46 +01:00
dependabot[bot]
0883882c3b
Bump verif/core-v-verif from 79d03a5 to aa5fe84 ( #1806 )
2024-02-05 23:37:08 +01:00
JeanRochCoulon
de5d0d7ed4
cv32a65x ( #1799 )
2024-02-01 13:11:45 +01:00
JeanRochCoulon
56f6216430
Run simulation for embedded configuration ( #1798 )
2024-01-30 11:06:54 +01:00
dependabot[bot]
ae3a1ead28
Bump verif/core-v-verif from f17b93a to 79d03a5 ( #1797 )
2024-01-29 22:46:26 +01:00
dependabot[bot]
1e78cc8e6e
Bump verif/core-v-verif from 752e67f to f17b93a ( #1789 )
...
Bumps [verif/core-v-verif](https://github.com/openhwgroup/core-v-verif ) from `752e67f` to `f17b93a`.
- [Release notes](https://github.com/openhwgroup/core-v-verif/releases )
- [Commits](752e67f54c...f17b93a693
2024-01-26 16:44:56 +00:00
Jalali
c2d9d4b283
MTVAL : Remove MTVAL CSR from CVA6 UVM environment ( #1788 )
2024-01-26 16:47:15 +01:00
Jalali
179084315f
ISACOV : Update seq Directed test, and remove failing tests from regression ( #1787 )
2024-01-26 15:02:31 +01:00
Guillaume Chauvon
e0ca60169b
Fix path for vcs init_testharness.do ( #1780 )
2024-01-24 17:49:02 +01:00
Jalali
358a73a07d
Enable zcb extension into cva6 UVM env ( #1777 )
2024-01-24 15:37:18 +00:00
dependabot[bot]
6568b18a54
Bump verif/core-v-verif from 0ea56b3 to 752e67f ( #1776 )
2024-01-23 16:01:03 +01:00
Jalali
cabbaf690d
Exclude cva6_rvfi_combi module from Code coverage ( #1773 )
2024-01-22 17:16:02 +01:00
Siris Li
ef5e378c93
Fix bug in install-spike.sh ( #1763 )
2024-01-18 23:32:32 +01:00
Yannick Casamatta
0ce6b40b26
Remove all logic and sequential related to RVFI in CORE cva6 ( #1762 )
2024-01-18 22:51:10 +01:00
MarioOpenHWGroup
8b6e8295f8
Add priv level to cva6.py and fix smoke-tests ( #1768 )
2024-01-17 23:14:19 +01:00
