André Sintzoff
f0887e4ec5
commit_stage.sv: add condition before Zcmp code ( #1932 )
2024-03-15 18:16:33 +01:00
André Sintzoff
9a713c3b17
smoke-tests.sh: run first I-ADD-01 test for cv64a6_imafdc_sv39 ( #1934 )
2024-03-15 18:14:32 +01:00
Jalali
6851499b18
Add directed Tests for jump instructions ( #1933 )
2024-03-15 15:16:21 +00:00
valentinThomazic
9f228c396a
Fix FPGA build report in Gitlab CI ( #1931 )
...
Fixed a typo in the fpga build job (introduced by fd12ee5
2024-03-15 13:55:35 +00:00
valentinThomazic
fd12ee596c
Add smoke-tests and fpga logs on dashboard ( #1928 )
2024-03-14 14:43:56 +01:00
Rohan Arshid
94f6528e1f
[Docs] Add Zcmp Instructions in CVA6 user guide and requirement specifications ( #1927 )
2024-03-13 22:52:44 +01:00
Côme
aed4ed7c23
move functions into modules ( #1926 )
2024-03-13 17:46:33 +01:00
Rohan Arshid
c827c3b770
Zcmp extension support ( #1779 )
2024-03-13 11:37:49 +01:00
Michael Platzer
91fe64b119
acc_dispatcher: Allow single-stepping of commit stage ( #1920 )
...
Gives the accelerator dispatcher the ability to single-step the
commit stage, which avoids retiring instructions on another
commit port than port 0.
2024-03-12 21:42:06 +01:00
JeanRochCoulon
57f062bd85
Add Caches submodule description in Design Doc ( #1923 )
2024-03-12 17:40:05 +01:00
JeanRochCoulon
378144ddc4
03 doc is deprecated ( #1922 )
...
GitHub Issues report 03 doc limitations. As it is not the main design document, we would like to notify that it is deprecated.
2024-03-12 16:36:27 +00:00
Côme
83d94bbb69
transform rvfi types into macros ( #1921 )
2024-03-12 17:34:27 +01:00
JeanRochCoulon
301f18a5f4
Improve FRONTEND description ( #1914 )
2024-03-11 12:52:35 +01:00
valentinThomazic
fde7e856e7
detect old versions of spike ( #1910 )
2024-03-08 23:54:05 +01:00
Côme
32a3cd56ee
Parametrization step 2 ( #1908 )
2024-03-08 22:53:42 +01:00
Jalali
bb2c6bd41f
Code coverage : Exclude unread module form CC (fix issue #1903 ) ( #1907 )
2024-03-08 18:35:01 +01:00
André Sintzoff
8c2bbb0527
cva6.py: fix typos in displayed messages ( #1906 )
2024-03-08 14:01:19 +01:00
valentinThomazic
392b08f2cf
Unshallow core-v-verif in smoke-gate test ( #1905 )
2024-03-08 11:18:08 +01:00
JeanRochCoulon
71b015622c
[HOTFIX] Fix tipo in README.md ( #1901 )
...
related to #1840
2024-03-07 18:54:37 +01:00
Yannick Casamatta
bc41a0b7fb
Modify rvfi probes for param change ( #1900 )
2024-03-07 18:34:27 +01:00
valentinThomazic
a4fc0e9f99
Check tools version before simulation ( #1899 )
2024-03-07 16:34:10 +01:00
Côme
13dfa744d2
Parametrization step 1 ( #1896 )
2024-03-06 17:02:55 +01:00
Cesar Fuguet
9267d14f2e
hpdcache: update submodule, interface and parameters ( #1893 )
2024-03-05 22:24:44 +01:00
Zbigniew Chamski
4fcdf4ea30
Generate separate per-target logs when simulating. ( #1870 )
2024-03-05 19:37:57 +01:00
valentinThomazic
fb86e7a5ac
Mark job as failed when build fails ( #1891 )
2024-03-05 17:57:32 +01:00
Zbigniew Chamski
16bdcda07c
Improve environment setup. Fix Verilator installation process. ( #1864 )
...
* verif/sim/setup-env.sh: Double-quote variable values. Install Verilator
in 'tools/verilator' by default. Add SPIKE_PATH to PATH.
* verif/regress/install-verilator.sh: By default use per-version dirs to
build and install Verilator. Add and improve configuration messages.
2024-03-05 17:18:33 +01:00
JeanRochCoulon
b3ae6e9362
Revert MMU ( #1890 )
...
* Revert "fix vcs simulation errors regarding hypervisor extension code (#1889 )"
This reverts commit 5ff5f164fb#1881 )"
This reverts commit 6a5863e71a#1876 )"
This reverts commit 9fb5db2555
2024-03-05 16:44:40 +01:00
AngelaGonzalezMarino
5ff5f164fb
fix vcs simulation errors regarding hypervisor extension code ( #1889 )
2024-03-05 14:36:08 +01:00
Jalali
9f928e4c12
Exceptions : Add bins for Read-only CSRs ( #1885 )
2024-03-05 14:17:56 +01:00
Jalali
f5662fb49f
ISA DVPLAN : Add bit-manipilation instructions (Zb*) ( #1884 )
2024-03-05 14:17:20 +01:00
AngelaGonzalezMarino
6a5863e71a
Mmu user manual ( #1881 )
...
* user manual update mmu v0
* Include information for hypervisor extension use. Fix issue in satp mode bits.
* Remove old text
2024-03-05 13:50:45 +01:00
JeanRochCoulon
f9e6a22960
[HOTFIX] Fix ras.sv ( #1887 )
2024-03-05 13:32:39 +01:00
JeanRochCoulon
483ef90127
Update frontend module description ( #1882 )
2024-03-04 23:18:27 +01:00
MarioOpenHWGroup
a3dd9a708d
Use cva6.py in github ci ( #1874 )
2024-03-01 10:52:34 +01:00
AngelaGonzalezMarino
9fb5db2555
Mmu unify pr ( #1876 )
2024-02-29 22:03:56 +01:00
Jalali
ce0ab81630
Connect CSRs info from RVFI_CSR in the testbench & update simulation target ( #1879 )
2024-02-28 16:20:24 +01:00
dependabot[bot]
5dceb0d57a
Bump core/cache_subsystem/hpdcache from 019e04f to 5dea9e0 ( #1877 )
2024-02-26 21:24:56 +01:00
Yannick Casamatta
1dec79464e
add csr in rvfi ( #1833 )
2024-02-24 00:10:23 +01:00
CoralieAllioux
68f952b44c
Update usage of riscv_instr_gen_tb_top as in other cores: adapt it in corev-dv to import cva6-dependent packages ( #1862 )
2024-02-23 23:28:10 +01:00
André Sintzoff
1474395869
decoder.sv: sfence.vma valid only if S mode supported ( fix #1866 ) ( #1869 )
2024-02-23 23:10:40 +01:00
JeanRochCoulon
f332688fc0
Complete Design Document ( #1865 )
2024-02-23 23:09:11 +01:00
valentinThomazic
e2a5b80550
do not source smoke-tests in ci ( #1868 )
2024-02-23 18:06:20 +01:00
Jalali
514fb86738
Map AXI functional coverage to the HVP ( #1867 )
2024-02-23 18:04:58 +01:00
Jalali
9c4a3c37d6
Remove mcountinhibit from csr_test and UVM env ( #1863 )
2024-02-21 19:13:57 +01:00
André Sintzoff
71f57a38c2
csr_regfile.sv: no MENVCFG[H], MCOUNTEREN when no User mode ( fix #1843 ) ( #1861 )
2024-02-21 18:16:35 +01:00
André Sintzoff
3cdc903a3a
csr_regfile.sv: mcountinhibit only when PERF_COUNTER_EN ( fix #1844 ) ( #1860 )
2024-02-21 14:13:50 +01:00
dependabot[bot]
e70bcbd6e7
Bump core/cache_subsystem/hpdcache from 38b9318 to 019e04f ( #1857 )
2024-02-21 13:14:03 +01:00
dependabot[bot]
21deaa71dc
Bump verif/core-v-verif from 1955db4 to d466330 ( #1858 )
...
Bumps [verif/core-v-verif](https://github.com/openhwgroup/core-v-verif ) from `1955db4` to `d466330`.
- [Release notes](https://github.com/openhwgroup/core-v-verif/releases )
- [Commits](1955db4ef7...d46633081b
2024-02-21 11:17:10 +00:00
Luca Valente
c84f979a15
Enable reads on CSR_HPM_COUNTERx ( #1824 )
2024-02-21 09:44:51 +01:00
Jalali
5dd04829e3
ISA functional coverage : Add directed tests ( #1855 )
2024-02-21 09:31:54 +01:00
