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cva6/core
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Nils Wistoff aeb0b646bf
cache_ctrl: Generalise AXI offset generation (#2573) 
For `XLEN = 64`, some tools (e.g. VCS) still elaborate the offset generation block for `XLEN = 32`, throwing an elaboration error (illegal bit access). Fix this by generating the AXI offset in an equivalent, parameter-agnostic and tool-friendly way.
2024-11-04 09:24:57 +01:00
..
cache_subsystem cache_ctrl: Generalise AXI offset generation (#2573) 2024-11-04 09:24:57 +01:00
cva6_mmu Revert "[PMP] Extracted PMP (#2476)" (#2524) 2024-10-04 07:39:35 +02:00
cvfpu@3116391bf6 Cvfpu from vendor to submodule (#2070) 2024-04-23 14:54:42 +02:00
cvxif_example Fixes and Update CVXIF non regression tests, regression and TB (#2424) 2024-08-01 16:06:24 +02:00
frontend Fix: Replace riscv_pkg:VLEN by CVA6Cfg.VLEN 2024-10-23 18:24:38 +02:00
include Declare VLEN as new CVA6 parameter 2024-10-23 18:24:38 +02:00
pmp Revert "[PMP] Extracted PMP (#2476)" (#2524) 2024-10-04 07:39:35 +02:00
acc_dispatcher.sv acc_dispatcher: don't issue instruction from buffer if flushing (#2490) 2024-11-01 17:04:12 +01:00
alu.sv Increase code coverage on second ALU by removing branch logic (#2362) 2024-08-26 17:32:24 +02:00
amo_buffer.sv Parameterization and other fixes for downstream project (#1950) 2024-04-05 13:02:18 +02:00
ariane_regfile.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
ariane_regfile_ff.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
ariane_regfile_fpga.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
axi_shim.sv Parametrization step 3 part 2 (#1939) 2024-03-18 12:06:55 +01:00
branch_unit.sv spyglass: move assignments in if clause as only used there (#2444) 2024-08-13 17:11:10 +02:00
commit_stage.sv increase code coverage in commit stage (#2555) 2024-10-18 07:02:07 +00:00
compressed_decoder.sv spyglass: remove useless assignments (#2439) 2024-08-12 15:06:39 +02:00
controller.sv Move DCacheType to config struct (#2025) 2024-04-10 23:26:21 +02:00
csr_buffer.sv Parametrization step 3 part 3 (last) (#1940) 2024-03-18 16:19:52 +01:00
csr_regfile.sv Fix pmpaddr read logic considering G=2 (#2469) 2024-10-23 08:54:25 +02:00
cva6.sv Use uvm testbench to run gate simulations (#2548) 2024-10-16 07:08:59 +02:00
cva6_accel_first_pass_decoder_stub.sv Fix SuperScalar config and add CVA6Cfg to first pass decoder (#2047) 2024-04-17 16:34:08 +02:00
cva6_fifo_v3.sv Verible reformat (#2014) 2024-04-08 11:26:08 +02:00
cva6_rvfi.sv Code clean-up of the number of register address bits (#2483) 2024-08-30 17:22:53 +02:00
cva6_rvfi_probes.sv superscalar: make SuperscalarEn a CVA6Cfg attribute (#2322) 2024-07-05 14:09:48 +02:00
cvxif_compressed_if_driver.sv CVXIF 1.0.0 (#2340) 2024-07-12 10:53:18 +02:00
cvxif_fu.sv Fixes and Update CVXIF non regression tests, regression and TB (#2424) 2024-08-01 16:06:24 +02:00
cvxif_issue_register_commit_if_driver.sv Separate RAW and WAW process to fix CVXIF with Superscalar (#2395) 2024-07-26 14:58:18 +02:00
decoder.sv spyglass: remove W528 warnings in decoder.sv (#2503) 2024-09-19 15:45:36 +02:00
ex_stage.sv Increase code coverage on second ALU by removing branch logic (#2362) 2024-08-26 17:32:24 +02:00
Flist.cva6 Revert "[PMP] Extracted PMP (#2476)" (#2524) 2024-10-04 07:39:35 +02:00
Flist.cva6_gate CVXIF 1.0.0 (#2340) 2024-07-12 10:53:18 +02:00
fpu_wrap.sv Make D independent on xlen (#2005) 2024-05-12 20:15:50 +02:00
id_stage.sv CVXIF 1.0.0 (#2340) 2024-07-12 10:53:18 +02:00
instr_realign.sv Fix: Replace riscv_pkg:VLEN by CVA6Cfg.VLEN 2024-10-23 18:24:38 +02:00
issue_read_operands.sv [HOTFIX] Fix Handling of CVXIF instruction being interrupted (#2537) 2024-10-09 16:34:45 +02:00
issue_stage.sv Refactor forwarding in issue_stage module (#2519) 2024-10-01 06:13:30 +02:00
load_store_unit.sv Revert "[PMP] Extracted PMP (#2476)" (#2524) 2024-10-04 07:39:35 +02:00
load_unit.sv condition load and store modules (#2349) 2024-07-13 09:32:51 +02:00
lsu_bypass.sv Parametrization step 2 (#1908) 2024-03-08 22:53:42 +01:00
macro_decoder.sv Parametrization step 3 part 3 (last) (#1940) 2024-03-18 16:19:52 +01:00
mult.sv Parametrization step 3 part 3 (last) (#1940) 2024-03-18 16:19:52 +01:00
multiplier.sv Parametrization step 3 part 3 (last) (#1940) 2024-03-18 16:19:52 +01:00
perf_counters.sv Parametrize MHPMCounterNum inside core/perf_counters.sv (#1949) 2024-03-25 11:37:54 +01:00
scoreboard.sv Refactor forwarding in issue_stage module (#2519) 2024-10-01 06:13:30 +02:00
serdiv.sv spyglass: remove WRN_1024 warnings (#2448) 2024-08-19 15:44:30 +02:00
store_buffer.sv Parametrization step 3 part 3 (last) (#1940) 2024-03-18 16:19:52 +01:00
store_unit.sv Code clean-up of the number of register address bits (#2483) 2024-08-30 17:22:53 +02:00