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85 commits

Author SHA1 Message Date
Olof Kindgren
fda7dd288a Optimize enable signal for mem_if buffers 2020-04-15 22:48:28 +02:00
Olof Kindgren
1d311edb7d Make counter internal in serv_state 2020-04-15 10:29:50 +02:00
Olof Kindgren
9a8dcde030 Simplify o_dbus_adr assignment 2020-04-03 22:58:24 +02:00
Olof Kindgren
6b0e4fb3ea Disable misalignment traps when CSR is disabled 2020-03-27 08:55:34 +01:00
Olof Kindgren
726e520cce Fix lint warnings when CSR is disabled 2020-03-25 23:32:12 +01:00
Olof Kindgren
3e9e25e984 Avoid resetting bufreg 2020-03-03 09:21:55 +01:00
Olof Kindgren
b48b02b8df Add parameter to disable CSR/interrupts 
Also disables timer in servant if CSR/interrupts are disabled
 2020-03-02 16:17:26 +01:00
Olof Kindgren
7f16f17ca5 Optimize CSR immediate handling 2020-02-19 10:02:48 +01:00
Olof Kindgren
36746d3890 Remove unused signals 2020-02-17 23:01:49 +01:00
Olof Kindgren
5aa1fbe709 Stop depending on run state 2019-12-08 22:51:28 +01:00
Olof Kindgren
6067b0e684 Use one-hot encoding for ALU rd sel 2019-12-07 23:36:36 +01:00
Olof Kindgren
eb5d25ea1c Move op_b mux to alu 2019-12-07 23:09:04 +01:00
Olof Kindgren
e93fd0d30e Fix compile errors with RISCV_FORMAL 2019-12-04 23:42:40 +01:00
Olof Kindgren
8b82c85fb6 Create toplevel without RF 2019-11-20 18:26:04 +01:00
Olof Kindgren
4532c8dafd Move rd selection to rf_if 2019-11-20 18:26:04 +01:00
Olof Kindgren
04037c4354 Split out RF to separate module 2019-11-20 18:26:04 +01:00
Olof Kindgren
40000cbeb9 Fix IRQ 
This contains a lot of fixes as IRQ support was broken on both
RTL and zephyr side

* Interrupts are now synced to instruction lifetimes
* Interrupts are disabled on traps and mie is pushed to mpie
* Zephyr applications regenerated from rewritten Zephyr port
* Timer is 32-bit to avoid wrapping around too often
* MEPC was not read properly from CSR storage
 2019-11-19 11:06:50 +01:00
Olof Kindgren
98bfcc3b62 Remove unused jalr signal 2019-10-30 09:07:58 +01:00
Olof Kindgren
75decc8251 Bring back old immediate decoder 
This was originally thrown out since it was slow and cost too much
resources. Due to other changes in the core, it is now cheaper
than the other one
 2019-10-29 21:54:22 +01:00
Olof Kindgren
8bc54a99ad Move mcause generation to serv_csr 2019-09-26 23:36:02 +02:00
Olof Kindgren
2b5c71fe9b Gate mem_rd in mem_if 2019-09-26 23:31:23 +02:00
Olof Kindgren
0f767ad2d3 Gate mem_misalign in mem_if 2019-09-26 23:23:42 +02:00
Olof Kindgren
126937f16a Rewrite RF and state machine 
Big patch, but would take more work to split it up
 2019-09-26 23:09:22 +02:00
Olof Kindgren
8481fb46a1 Remove dead code 2019-09-26 22:59:46 +02:00
Olof Kindgren
ca2beaf786 Pass rf_rreq through serv_state 2019-09-26 22:59:46 +02:00
Olof Kindgren
3d6eb3feca Separate rf_ready and dbus_ack 2019-09-26 22:59:46 +02:00
Florian Zaruba
27621a285e rtl: Make compatible to Synopsys Design Compiler 
Synopysis DC has problems with forward references and initial
statements. Fixed that for better compatibility.
 2019-09-26 22:57:40 +02:00
Olof Kindgren
920ad92bc7 Remove unused rs_en signal 2019-09-16 10:45:42 +02:00
Olof Kindgren
d4c782bce6 Set o_dbus_we directly from decode 2019-09-16 00:13:21 +02:00
Olof Kindgren
5a44634ee5 Avoid exposing funct3 from decode 2019-09-15 23:50:02 +02:00
Olof Kindgren
9575eb4fef Separate decode and state 2019-09-15 23:25:10 +02:00
Olof Kindgren
7289a68f6e Separate state from o_bufreg_loop 2019-09-14 22:52:41 +02:00
Olof Kindgren
1248043a39 Separate state and decode from CSR signals 2019-09-14 22:18:03 +02:00
Olof Kindgren
ef3fc9274d Rename misleading signal names 2019-09-13 23:30:46 +02:00
Olof Kindgren
8c63a1a22f Simplify bufreg.i_clr 2019-09-13 23:30:46 +02:00
Olof Kindgren
8dc137fb07 Kill of mem_init and mem_en 2019-09-13 23:30:46 +02:00
Olof Kindgren
e20e0eef8f Optimize dbus_cyc 2019-09-13 23:30:46 +02:00
Olof Kindgren
a0ba84096a Simplify csr stuff 2019-09-13 23:30:46 +02:00
Olof Kindgren
7425128dd8 Pass imm offsets through bufreg 2019-09-13 23:30:46 +02:00
Olof Kindgren
28a2bbdb60 Rename misleading signal name 2019-09-13 23:30:46 +02:00
Olof Kindgren
286a07bfc8 Mask rvfi_valid during reset release 2019-09-13 23:30:45 +02:00
Olof Kindgren
d2cf7e547a Interrupt refactoring 2019-08-25 22:47:29 +02:00
Olof Kindgren
3c1582b7b2 Remove unused RVFI defines 2019-08-14 22:15:45 +02:00
Olof Kindgren
892388627c Speed up memory accesses 2019-08-14 22:15:45 +02:00
Olof Kindgren
31852f175d Simplify alu_cmp_eq control logic 2019-07-23 12:10:38 +02:00
Olof Kindgren
af3b82f9ac Optimize take_branch condition 2019-07-23 12:10:38 +02:00
Olof Kindgren
16c93a58ee Move mepc and mtval into RF memory 2019-07-08 07:49:58 +02:00
AlAlves
2fb56ac62d Update serv_top.v 2019-07-08 07:47:12 +02:00
Olof Kindgren
e107627e71 Reduce warnings 2019-06-24 15:22:08 +02:00
Olof Kindgren
42ac1e5e4d Store CSR in RF RAM 
Since FPGA uses fixed-size RAM, it's better in most cases to store
the CSR in unused memory positions in that RAM.

Since the decoding is made more complex, the old register file
implementation is kept around since that is more efficient when we
don't want CSR and potentially when the FPGA support hardware
shift registers.
 2019-06-07 19:39:18 +02:00