973 commits

Author	SHA1	Message	Date
Blaise Tine	5c83c594c1	minor update	2021-01-07 17:25:59 -08:00
Blaise Tine	4eb85dd97a	minor update	2021-01-06 23:37:24 -08:00
Blaise Tine	ba1082249a	minor update	2021-01-06 23:30:30 -08:00
Blaise Tine	8aea9cbe07	minor update	2021-01-06 21:39:15 -08:00
Blaise Tine	146c285aa0	minor update	2021-01-06 19:59:04 -08:00
Blaise Tine	2b8435471a	speeding up simulation using dedicated full dpi-based FPU core	2021-01-06 18:44:06 -08:00
Blaise Tine	2058718f0f	minor updates	2021-01-06 07:18:14 -08:00
Blaise Tine	31ff70fd4e	minor updates	2021-01-05 15:03:41 -08:00
Blaise Tine	846a4036d3	minor update	2021-01-05 05:46:20 -08:00
Blaise Tine	39bff921be	cache bug fixes	2021-01-05 05:04:49 -08:00
Blaise Tine	762b8e2e3e	fixed cache mshr critical path	2021-01-04 12:49:40 -05:00
Blaise Tine	9a077b97f3	Merge branch 'master' of https://github.gatech.edu/casl/Vortex	2021-01-03 23:11:06 -05:00
Blaise Tine	4d55118545	cache pipeline optimization - moved tag access to stage0	2021-01-03 23:10:41 -05:00
Blaise Tine	4bc3b537bd	fixed reset fan-out	2021-01-03 20:06:36 -08:00
Blaise Tine	9cef1aae04	cache fill response address is the mshr's top address, no need to store it	2021-01-03 00:57:24 -05:00
Blaise Tine	4815ab099c	using single-port block ram for cache tags, restoring core reset signal	2021-01-02 19:53:41 -08:00
Blaise Tine	a825941f51	Merge branch 'master' of https://github.gatech.edu/casl/Vortex	2021-01-02 16:06:09 -05:00
Blaise Tine	2d69ca5d67	scratchpad optimization for stack access using custom bank offset aligned to stack size	2021-01-02 16:00:00 -05:00
Blaise Tine	93c36273fa	minor update	2021-01-01 20:24:18 -08:00
Blaise Tine	da9649c2a3	fixed pipe register reset issue in synthesis	2021-01-01 14:54:18 -08:00
Blaise Tine	c5cf494e72	Merge branch 'master' of https://github.gatech.edu/casl/Vortex	2021-01-01 11:46:45 -08:00
Blaise Tine	36602cfa6a	buffering core reset signal	2021-01-01 11:46:30 -08:00
Blaise Tine	30d950ada2	vx_spawn_warps redesign using opencl's style scheduler	2021-01-01 14:13:48 -05:00
Blaise Tine	138db29310	Merge branch 'master' of https://github.gatech.edu/casl/Vortex	2020-12-31 22:40:34 -05:00
Blaise Tine	e4a00dd0d9	fixed loader script stack setup	2020-12-31 22:37:20 -05:00
Blaise Tine	b2cfde5d6d	enabling shared memory back	2020-12-31 19:19:14 -08:00
Blaise Tine	abe32ed553	cache optimization - moved read requests to stage1 and eliminating stage3	2020-12-31 07:40:58 -08:00
Blaise Tine	9f128085d5	scoreboard optimization - using writeback's end-of-packet status	2020-12-30 06:47:56 -08:00
Blaise Tine	e431162347	minor update	2020-12-30 04:09:21 -08:00
Blaise Tine	d44144f72f	FPU float<->int conversion optimization	2020-12-29 15:37:45 -08:00
Blaise Tine	e83c4638a0	FPU area optimization sharing fmadd hard block	2020-12-27 17:31:10 -08:00
Blaise Tine	25df233005	Adding Altera Stratix 10 support	2020-12-27 10:44:57 -08:00
Blaise Tine	b2b8f190dd	minor update	2020-12-26 14:47:41 -08:00
Blaise Tine	33c431ed44	multiplier unit optimization - using fifo for metadata, shift register optimization	2020-12-26 11:23:21 -08:00
Blaise Tine	b459192dec	critical path optimization - fpga fmax @4c = ~212 mhz	2020-12-26 03:28:32 -08:00
Blaise Tine	3fdc49971c	minor update	2020-12-24 09:22:44 -08:00
Blaise Tine	703a861fe9	added support for write-through cache, removed cache snooping support	2020-12-23 23:51:02 -08:00
Blaise Tine	d956e268b9	adding new performance counters (banks utilization and DRAM bus utilization)	2020-12-22 12:33:45 -08:00
Blaise Tine	4b7d871d62	allowing partial cache request submissions, io bus support broken	2020-12-21 03:53:13 -08:00
Blaise Tine	4bbd7bf408	performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,	2020-12-19 02:45:06 -08:00
Blaise Tine	29cd2f5dff	fixed register file initialization to zero synthesis inference	2020-12-10 00:27:56 -08:00
Blaise Tine	3e9abb978b	fixed typo	2020-12-09 13:03:22 -08:00
Blaise Tine	fe07ca9aee	minor update	2020-12-09 05:49:02 -08:00
Blaise Tine	e0905f8352	minor update	2020-12-09 05:34:27 -08:00
Blaise Tine	d81ce8b609	minor update	2020-12-09 00:57:31 -08:00
Blaise Tine	12f7fcfa75	adding missing files, buffering teh snoop forwarder	2020-12-09 00:24:32 -08:00
Blaise Tine	d5438fd591	merging perf counters	2020-12-08 21:02:39 -08:00
Blaise Tine	14baec86d5	moved apae sources into rtl/afu	2020-12-08 04:59:11 -08:00
Blaise Tine	d5fa82f5e4	cache req datapath optimizations	2020-12-08 02:58:08 -08:00
Xandy Liu	1595ff08e2	PERF pipeline stalls and cache	2020-12-08 01:14:41 -05:00