github-mirrors/cva5
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva5.git synced 2025-04-19 19:47:23 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions
580 commits 2 branches 1 tag 11 MiB
Commit graph

580 commits

This branch
This branch
All branches
Author SHA1 Message Date
Eric Matthews
2e77b891d5 Add a writeback port for the LS unit 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2023-01-20 12:53:56 -05:00
Eric Matthews
b275bd9691 Split write-back muxes into seperate instances 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2023-01-19 15:16:38 -05:00
Eric Matthews
ebcddd904a move the zero register handling from writeback to decode 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2023-01-19 12:14:53 -05:00
Eric Matthews
7fda9f9e1f renamer LUTRAM restructure 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2023-01-19 12:13:55 -05:00
Eric Matthews
fb301bf462 writeback code cleanup 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2023-01-19 12:13:02 -05:00
Eric Matthews
dea43dc7ca Store Queue refactor 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2023-01-19 12:12:40 -05:00
Eric Matthews
b5f792048b Add nexys 7 example 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-11-14 13:59:24 -05:00
Eric Matthews
3e691efb37 Switch L1 arbitration to round-robin 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-11-14 13:36:50 -05:00
Eric Matthews
4d42d3445d Simulation tracing improvements 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-11-14 12:03:35 -05:00
Eric Matthews
7de7e1a5c0 Linting fix 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-11-14 11:38:41 -05:00
Eric Matthews
2339ae182c Adds support for more than 2 regfile read ports 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-11-14 11:38:15 -05:00
Eric Matthews
8008679a7a dcache re-organization for load/store address overlap 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-11-14 11:35:56 -05:00
Florian Meisel
ee668917c8 l2_arbiter - Fix mem_data FIFO width 
Signed-off-by: Florian Meisel <meisel@esa.tu-darmstadt.de>
 2022-09-09 16:57:55 +02:00
Florian Meisel
f6a593402a Update uses of l2_requester_interface::be 
-> examples/litex/l1_to_wishbone.sv
-> test_benches/verilator/AXI_DDR_simulation/axi_l2_text.sv, .cc

Signed-off-by: Florian Meisel <meisel@esa.tu-darmstadt.de>
 2022-09-09 16:57:55 +02:00
Florian Meisel
6b1d2280d8 l2,axi_to_arb: Move be (wstrb) to data FIFO 
Fix: If the AXI bus has WREADY=0 and AWREADY=1,
  the AW handshake (single beat) that CVA5 starts
  concurrently with the corresponding W handshake
  will complete first.
 CVA5 stores `be` (-> WSTRB) in the FIFO for AW requests,
  even though WSTRB is part of the W handshake.
 The result is that WSTRB becomes unstable once the AW request finishes.
-> The fix moves `be` to the write data FIFO.

Signed-off-by: Florian Meisel <meisel@esa.tu-darmstadt.de>
 2022-09-09 16:57:55 +02:00
Eric Matthews
7cb0b39ab0 Increase write throughput for single word bursts 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-07-05 15:50:06 -04:00
Eric Matthews
7606dd927b Add phys_addr to unit issue/writeback interfaces 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-07-05 15:48:22 -04:00
Eric Matthews
95bc8d244c Reduce data cache latency 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-07-05 15:38:36 -04:00
Eric Matthews
fe3c0384fc Rework instruction cache addressing logic 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-07-05 15:08:38 -04:00
Eric Matthews
e6fbbcfeb2 Fix for FIFO power-of-two constraint 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-06-13 14:45:57 -04:00
Eric Matthews
562a9c2ff6 Instruction and Data Cache reorganization and cleanup 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-06-13 14:45:20 -04:00
Eric Matthews
6aeac17b9d Rework simulation stats 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-27 16:28:17 -04:00
Mike Thompson
3239e20360
Merge pull request #5 from e-matthews/minor-fixes 
Minor fixes
 2022-05-26 13:17:14 -04:00
Eric Matthews
ce38554595 Add interrupt/CSR support to LiteX minimal config 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-25 10:44:38 -04:00
Eric Matthews
7bf90023f0 Fix 1-way dcache support 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-18 15:13:14 -04:00
Eric Matthews
207c47abd7 Fix AXI support for independent icache/dcache line widths 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-16 16:48:35 -04:00
Mike Thompson
b4d6a9fa29
Merge pull request #4 from e-matthews/litex 
Fetch and Load-Store Interface Refactor and LiteX Support
 2022-05-16 15:19:30 -04:00
Eric Matthews
b2e425abed Added LiteX support 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-16 14:09:17 -04:00
Eric Matthews
2290527612 Interrupt fixes 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-16 13:35:55 -04:00
Eric Matthews
28dc5bc43b Store-queue cleanups 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-16 13:33:30 -04:00
Eric Matthews
1ffbacbb51 verilator optional PC trace support 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-12 22:22:45 -04:00
Eric Matthews
bae3594995 load-store-queue code cleanup 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-12 22:21:52 -04:00
Eric Matthews
b87cb6ca16 load-store code cleanup 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-12 10:46:10 -04:00
Eric Matthews
a3d362b9ac dtagbank code cleanup 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-11 15:04:37 -04:00
Eric Matthews
f48faa43f2 Code cleanup 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-11 13:21:05 -04:00
Eric Matthews
331842f1b3 Added dcache uncachable region support 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-11 13:20:24 -04:00
Eric Matthews
00b0c9e3dd Wishbone bus code cleanup 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-11 13:15:57 -04:00
Eric Matthews
d30e8fcfac Move fetch flush support outside of subfetch units 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-11 13:14:47 -04:00
Eric Matthews
0855bb623a Fixed support for subfetch units with maximum address ranges 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-11 13:12:19 -04:00
Eric Matthews
8c1059f395 Added instruction bus address mapping to branch predictor 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-11 13:10:53 -04:00
Eric Matthews
fb292ecd54 LFSR index lookup changed for Verilator 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-05-04 17:32:01 -04:00
Eric Matthews
087766b3bc Wishbone bus signals renamed 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-04-29 13:59:10 -04:00
Eric Matthews
08e59f20eb Added support for optional instruction buses 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-03-31 16:38:30 -04:00
Eric Matthews
49645ba103 code cleanups 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-03-31 13:48:51 -04:00
Eric Matthews
90c9dd6343 unified fetch and load-store sub_unit interfaces 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-03-25 13:27:07 -04:00
Eric Matthews
1f0a43e5f1 linting changes 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-03-24 21:09:33 -04:00
Eric Matthews
2ea13a9234 restructured load muxing 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-03-22 19:29:11 -04:00
Mike Thompson
14c4be99e7
Merge pull request #3 from e-matthews/rename 
Taiga to CVA5 renaming
 2022-03-07 16:41:14 -05:00
Eric Matthews
64e8e59e8a xilinx packaging updates 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-03-07 10:50:32 -08:00
Eric Matthews
9cff8c5afb renamed occurrences of taiga to cva5 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-03-05 12:53:49 -08:00