André Sintzoff
|
9bd5667992
|
decoder.sv: fix ZEXT.H instruction (fix #1758, #1975, #2010) (#2032)
- add missing ZEXT.H for RV64
- fix ZEXT.H for RV32: bit[24:20] shall be 0
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2024-04-11 16:38:11 +02:00 |
|
JeanRochCoulon
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527a989542
|
Clean-up 65x config_pkg.sv file by removing the localparams (#2031)
|
2024-04-11 11:29:31 +02:00 |
|
Côme
|
d6c37051c3
|
fix util/user_config.py for DCacheType (#2028)
|
2024-04-10 23:53:07 +02:00 |
|
Florian Zaruba
|
ecd6ed6b6b
|
Move DCacheType to config struct (#2025)
|
2024-04-10 23:26:21 +02:00 |
|
Jalali
|
bfff84eaeb
|
Fix issue #2018 (#2023)
|
2024-04-09 17:43:21 +02:00 |
|
Moritz Schneider
|
fa2cea2d65
|
Fix PMPCFG WARL behavior (#2019)
|
2024-04-09 16:40:00 +02:00 |
|
Côme
|
1c529d68ce
|
superscalar: return 2 instructions from instruction queue (#2022)
|
2024-04-09 16:39:24 +02:00 |
|
Côme
|
512296b9be
|
ci: perform synthesis on cv32a6_embedded only (#2021)
|
2024-04-09 11:17:44 +02:00 |
|
JeanRochCoulon
|
f4ec364bf4
|
Fix MIE CSR described in #2004 and #2008 Github issue (#2017)
|
2024-04-08 19:54:55 +02:00 |
|
Moritz Schneider
|
90d780eb14
|
Fix PMP CSR locked behavior (#2015)
|
2024-04-08 14:01:14 +02:00 |
|
valentinThomazic
|
4f73867fce
|
Do not add spike param arg if no spike param provided (#2016)
|
2024-04-08 12:03:20 +02:00 |
|
JeanRochCoulon
|
80e6d7cffc
|
Verible reformat (#2014)
|
2024-04-08 11:26:08 +02:00 |
|
Côme
|
ec44b22920
|
superscalar: fetch 64 bits (#2013)
|
2024-04-08 11:25:39 +02:00 |
|
JeanRochCoulon
|
c6f81d74c4
|
Remove parametrization Warning in README.md (#2011)
As th ebig change due to parametrization is over, I propose to remove the warning.
|
2024-04-08 10:33:28 +02:00 |
|
Cesar Fuguet
|
83a5b05752
|
hpdcache: update submodule (#2009)
|
2024-04-05 18:52:10 +02:00 |
|
Zbigniew Chamski
|
a6fc375dc6
|
[DVplans] Fix broken paths to VPTOOL. (#2007)
|
2024-04-05 18:21:39 +02:00 |
|
Florian Zaruba
|
38e8c059b2
|
Parameterization and other fixes for downstream project (#1950)
* Bender fixes and switch to `cva6_fifo_v3`
* cfg: Fix verilator warnings
* Bender: Fix yml
* acc_dispatcher: Add `csr_addr_i`
* parameterization: Fox AXI_USER_EN warning
* wb_cache: Fix Verilator Lint warnings
* cva6_fifo_v3: Add to Flist
* parameterization: Address review concerns
* Switch to `cva6_fifo_v3`
* tracer: Remove tracer interface
The interface made a bunch of problems with the
typedefs so I've removed it.
---------
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
|
2024-04-05 13:02:18 +02:00 |
|
Côme
|
f886713754
|
User config generator becomes a Python tool to work with configs (#2003)
|
2024-04-04 15:56:29 +02:00 |
|
Saute0212
|
5920e3d125
|
Add support for Nexys Video board (#1925)
|
2024-04-04 11:13:32 +02:00 |
|
valentinThomazic
|
5c7ddcbcc5
|
Fix log naming and dashboard improvements (#2001)
|
2024-04-03 18:03:47 +02:00 |
|
Zbigniew Chamski
|
73e181cdef
|
[Vendorized spec] Add ASCIIdoc inline anchors matching impl-def@1853796c. (#2002)
|
2024-04-03 18:03:33 +02:00 |
|
JeanRochCoulon
|
5fcc71b9d6
|
[HOT FIX] Use cva6_embedded for gate simulation (#1998)
|
2024-04-02 17:56:50 +02:00 |
|
JeanRochCoulon
|
4423feb06a
|
Rename ZiCondExtEn and FPGA_EN parameters (#1992)
|
2024-04-02 15:37:58 +02:00 |
|
dependabot[bot]
|
b401ab3868
|
Bump verif/core-v-verif from 64f8dc1 to 4f9dd2a (#1994)
|
2024-04-02 14:51:58 +02:00 |
|
valentinThomazic
|
3dc1f23a9d
|
Support Spike Parameters in cva6.py and bump core-v-verif (#1976)
|
2024-04-02 10:26:25 +02:00 |
|
dependabot[bot]
|
bcecaf1bdf
|
Bump verif/core-v-verif from 3630a6c to 54c6474 (#1990)
|
2024-04-01 22:41:57 +02:00 |
|
Jalali
|
ea2ccffa78
|
Functional coverage : no need for cvxif directed tests (#1969)
|
2024-03-29 15:41:13 +01:00 |
|
Guillaume Chauvon
|
f884347db4
|
Add debug_disable=1 to match default configuration of cva6.py (#1977)
|
2024-03-29 14:44:03 +01:00 |
|
JeanRochCoulon
|
8d6c1f709f
|
Modify the variable order inside the cva6_user_cfg_t (#1971)
Modify the variable order inside the cva6_user_cfg_t to gather extension params together and micro-architecture params together
|
2024-03-28 15:19:49 +01:00 |
|
dependabot[bot]
|
fbca195283
|
Bump verif/core-v-verif from 004b849 to 3630a6c (#1970)
|
2024-03-28 12:58:35 +01:00 |
|
JeanRochCoulon
|
64273ca4af
|
update Design Doc after bumping H extension (#1968)
|
2024-03-28 09:32:59 +01:00 |
|
Zbigniew Chamski
|
f73724b7e2
|
Vendorize RISC-V specs at tag 2023-10-02. (#1963)
* vendor/riscv/riscv-isa-manual: New vendorized repo.
* vendor/riscv_riscv-isa-manual.lock.hjson: Ditto.
* vendor/riscv_riscv-isa-manual.vendor.hjson: Ditto.
|
2024-03-25 17:52:43 +01:00 |
|
MarioOpenHWGroup
|
08d098bf51
|
[RVFI] Change CSR implementation (#1952)
|
2024-03-25 12:15:18 +01:00 |
|
Yannick Casamatta
|
5bc063131a
|
csr_regfile.sv: use CVA6Cfg.ASID_WIDTH instead of AsidWidth (fix cv64a6) (#1951)
|
2024-03-25 11:51:12 +01:00 |
|
Luca Valente
|
b45b52a38e
|
Parametrize MHPMCounterNum inside core/perf_counters.sv (#1949)
|
2024-03-25 11:37:54 +01:00 |
|
Bruno Sá
|
294ec96e76
|
Fix illegal instruction issue #1953 (#1955)
|
2024-03-25 07:26:42 +01:00 |
|
André Sintzoff
|
f846d8e638
|
cva6.py: use raw strings (#1959)
to avoid invalid escape sequence SyntaxWarning
since Python 3.12
|
2024-03-25 06:31:23 +01:00 |
|
CoralieAllioux
|
de2e254cd4
|
[Xcelium support] Remove void from DPI definition (#1856)
|
2024-03-22 17:07:06 +01:00 |
|
MarioOpenHWGroup
|
62bdf11594
|
Bump core-v-verif d94f0de and fix questa simulator (#1915)
|
2024-03-21 19:02:41 +01:00 |
|
Bruno Sá
|
86e1408666
|
Hypervisor extension (#1938)
Support 64bit H extension
|
2024-03-21 10:28:01 +01:00 |
|
Yannick Casamatta
|
9ecdaa1408
|
fix some bad assignments and lint warning related to RVFI feature (#1947)
|
2024-03-20 10:37:51 +01:00 |
|
JeanRochCoulon
|
c76b29a887
|
Update after parametrization changes (#1943)
|
2024-03-19 11:09:46 +01:00 |
|
dependabot[bot]
|
d0f411d178
|
Bump core/cache_subsystem/hpdcache from 8a13ec4 to 645e422 (#1942)
|
2024-03-18 20:30:40 +01:00 |
|
Côme
|
bd4b57cc64
|
Parametrization step 3 part 3 (last) (#1940)
|
2024-03-18 16:19:52 +01:00 |
|
Côme
|
4817575de9
|
Parametrization step 3 part 2 (#1939)
|
2024-03-18 12:06:55 +01:00 |
|
Rohan Arshid
|
b8ca8588cf
|
Updated Zcmp extension user guide and specification document (#1930)
|
2024-03-15 18:33:01 +01:00 |
|
Côme
|
987c645bb7
|
Parametrization step 3 (#1935)
This is the third step for #1451. Many values are moved but not all values are moved yet
* move NR_SB_ENTRIES & TRANS_ID_BITS
* remove default rvfi_instr_t from spike.sv
* fifo_v3: ariane_pkg::FPGA_EN becomes a param
* move FPGA_EN
* inline wt_cache_pkg::L15_SET_ASSOC
* move wt_cache_pkg::L15_WAY_WIDTH
* inline wt_cache_pkg::L1I_SET_ASSOC
* inline wt_cache_pkg::L1D_SET_ASSOC
* move wt_cache_pkg::DCACHE_CL_IDX_WIDTH
* move ICACHE_TAG_WIDTH
* move DCACHE_TAG_WIDTH
* move ICACHE_INDEX_WIDTH
* move ICACHE_SET_ASSOC
* use ICACHE_SET_ASSOC_WIDTH instead of $clog2(ICACHE_SET_ASSOC)
* move DCACHE_NUM_WORDS
* move DCACHE_INDEX_WIDTH
* move DCACHE_OFFSET_WIDTH
* move DCACHE_BYTE_OFFSET
* move DCACHE_DIRTY_WIDTH
* move DCACHE_SET_ASSOC_WIDTH
* move DCACHE_SET_ASSOC
* move CONFIG_L1I_SIZE
* move CONFIG_L1D_SIZE
* move DCACHE_LINE_WIDTH
* move ICACHE_LINE_WIDTH
* move ICACHE_USER_LINE_WIDTH
* move DCACHE_USER_LINE_WIDTH
* DATA_USER_WIDTH = DCACHE_USER_WIDTH
* move DCACHE_USER_WIDTH
* move FETCH_USER_WIDTH
* move FETCH_USER_EN
* move LOG2_INSTR_PER_FETCH
* move INSTR_PER_FETCH
* move FETCH_WIDTH
* transform SSTATUS_SD and SMODE_STATUS_READ_MASK into functions
* move [SM]_{SW,TIMER,EXT}_INTERRUPT into a structure
* move SV
* move vm_mode_t to config_pkg
* move MODE_SV
* move VPN2
* move PPNW
* move ASIDW
* move ModeW
* move XLEN_ALIGN_BYTES
* move DATA_USER_EN
* format: apply verible
|
2024-03-15 17:21:34 +00:00 |
|
André Sintzoff
|
f0887e4ec5
|
commit_stage.sv: add condition before Zcmp code (#1932)
|
2024-03-15 18:16:33 +01:00 |
|
André Sintzoff
|
9a713c3b17
|
smoke-tests.sh: run first I-ADD-01 test for cv64a6_imafdc_sv39 (#1934)
|
2024-03-15 18:14:32 +01:00 |
|
Jalali
|
6851499b18
|
Add directed Tests for jump instructions (#1933)
|
2024-03-15 15:16:21 +00:00 |
|