André Sintzoff
8070febca0
spyglass: remove W528 warnings in decoder.sv ( #2503 )
2024-09-19 15:45:36 +02:00
JeanRochCoulon
8ef28596d5
Code clean-up of the number of register address bits ( #2483 )
2024-08-30 17:22:53 +02:00
Guillaume Chauvon
8fa590b5c3
CVXIF 1.0.0 ( #2340 )
2024-07-12 10:53:18 +02:00
André Sintzoff
21733e55d7
decoder.sv: add checks for some B instructions ( fix #2276 ) ( #2282 )
2024-06-21 10:54:10 +02:00
JeanRochCoulon
dd763b4f4c
Rename FpuEn into RVF ( #2109 )
2024-05-15 09:16:44 +02:00
Asmaa Kassimi
807ed7825c
Add Supervisor condition under Interrupt control and remove else condition. ( #2098 )
2024-05-12 21:02:57 +02:00
Florian Zaruba
377b0de154
Fix SuperScalar config and add CVA6Cfg to first pass decoder ( #2047 )
...
* Add `CVA6Cfg` to first pass decoder
* Fix `verilator` `SELRANGE` warnings
* Update core/decoder.sv
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
* Update core/cva6_accel_first_pass_decoder_stub.sv
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
* Update core/decoder.sv
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
* Update core/frontend/instr_queue.sv
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
---------
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
2024-04-17 16:34:08 +02:00
André Sintzoff
9bd5667992
decoder.sv: fix ZEXT.H instruction ( fix #1758 , #1975 , #2010 ) ( #2032 )
...
- add missing ZEXT.H for RV64
- fix ZEXT.H for RV32: bit[24:20] shall be 0
2024-04-11 16:38:11 +02:00
JeanRochCoulon
4423feb06a
Rename ZiCondExtEn and FPGA_EN parameters ( #1992 )
2024-04-02 15:37:58 +02:00
Bruno Sá
294ec96e76
Fix illegal instruction issue #1953 ( #1955 )
2024-03-25 07:26:42 +01:00
Bruno Sá
86e1408666
Hypervisor extension ( #1938 )
...
Support 64bit H extension
2024-03-21 10:28:01 +01:00
Côme
bd4b57cc64
Parametrization step 3 part 3 (last) ( #1940 )
2024-03-18 16:19:52 +01:00
Côme
4817575de9
Parametrization step 3 part 2 ( #1939 )
2024-03-18 12:06:55 +01:00
Côme
987c645bb7
Parametrization step 3 ( #1935 )
...
This is the third step for #1451 . Many values are moved but not all values are moved yet
* move NR_SB_ENTRIES & TRANS_ID_BITS
* remove default rvfi_instr_t from spike.sv
* fifo_v3: ariane_pkg::FPGA_EN becomes a param
* move FPGA_EN
* inline wt_cache_pkg::L15_SET_ASSOC
* move wt_cache_pkg::L15_WAY_WIDTH
* inline wt_cache_pkg::L1I_SET_ASSOC
* inline wt_cache_pkg::L1D_SET_ASSOC
* move wt_cache_pkg::DCACHE_CL_IDX_WIDTH
* move ICACHE_TAG_WIDTH
* move DCACHE_TAG_WIDTH
* move ICACHE_INDEX_WIDTH
* move ICACHE_SET_ASSOC
* use ICACHE_SET_ASSOC_WIDTH instead of $clog2(ICACHE_SET_ASSOC)
* move DCACHE_NUM_WORDS
* move DCACHE_INDEX_WIDTH
* move DCACHE_OFFSET_WIDTH
* move DCACHE_BYTE_OFFSET
* move DCACHE_DIRTY_WIDTH
* move DCACHE_SET_ASSOC_WIDTH
* move DCACHE_SET_ASSOC
* move CONFIG_L1I_SIZE
* move CONFIG_L1D_SIZE
* move DCACHE_LINE_WIDTH
* move ICACHE_LINE_WIDTH
* move ICACHE_USER_LINE_WIDTH
* move DCACHE_USER_LINE_WIDTH
* DATA_USER_WIDTH = DCACHE_USER_WIDTH
* move DCACHE_USER_WIDTH
* move FETCH_USER_WIDTH
* move FETCH_USER_EN
* move LOG2_INSTR_PER_FETCH
* move INSTR_PER_FETCH
* move FETCH_WIDTH
* transform SSTATUS_SD and SMODE_STATUS_READ_MASK into functions
* move [SM]_{SW,TIMER,EXT}_INTERRUPT into a structure
* move SV
* move vm_mode_t to config_pkg
* move MODE_SV
* move VPN2
* move PPNW
* move ASIDW
* move ModeW
* move XLEN_ALIGN_BYTES
* move DATA_USER_EN
* format: apply verible
2024-03-15 17:21:34 +00:00
Côme
aed4ed7c23
move functions into modules ( #1926 )
2024-03-13 17:46:33 +01:00
Rohan Arshid
c827c3b770
Zcmp extension support ( #1779 )
2024-03-13 11:37:49 +01:00
Côme
32a3cd56ee
Parametrization step 2 ( #1908 )
2024-03-08 22:53:42 +01:00
André Sintzoff
1474395869
decoder.sv: sfence.vma valid only if S mode supported ( fix #1866 ) ( #1869 )
2024-02-23 23:10:40 +01:00
JeanRochCoulon
b4c287a18e
Design Document, add ID_STAGE description ( #1832 )
2024-02-16 16:17:46 +01:00
Guillaume Chauvon
fa101fae7a
Parameterize TVAL to reduce size in embedded ( #1784 )
2024-01-25 15:47:06 +01:00
Yannick Casamatta
0ce6b40b26
Remove all logic and sequential related to RVFI in CORE cva6 ( #1762 )
2024-01-18 22:51:10 +01:00
André Sintzoff
3afe870d78
csr_regfile.sv: add RVB field for MISA ( fix #1734 ) ( #1760 )
2024-01-15 14:34:25 +01:00
Gull Ahmed
8c14b6aa4a
resolving issue #1613 ( #1714 )
2023-12-17 17:59:22 +01:00
Côme
fab3255823
refactor(decoder): simplify interrupt indexing ( #1709 )
2023-12-14 14:36:17 +01:00
AEzzejjari
738d53af1c
Code coverage: condition RTL With parameters ( #1703 )
2023-12-13 07:52:47 +01:00
AEzzejjari
cbd3e9fe19
Modify coding style to improve CC ( #1672 )
2023-12-05 14:51:23 +01:00
MarioOpenHWGroup
220f534b6d
Spike Tandem Implementation using VCS simulator ( #1561 )
2023-11-09 19:29:24 +01:00
JeanRochCoulon
d087fd7c8a
[HOT FIX] Add else to SRET instruction decode ( #1595 )
...
Add the generation of illegal instruction in case of SRET decoding and supervisor mode disable
2023-11-06 08:21:12 +00:00
JeanRochCoulon
3fcb7b9c9b
Do not support DRET when DebugEn = 0 ( #1596 )
...
When debug mode is disable, DRET instruction is not supported.
2023-11-06 07:50:46 +00:00
Fatima Saleem
f14254dff6
removing zexth duplicated code for RV64 ( #1589 )
...
revert decoder.sv modifications done in a99f115d41
2023-11-02 09:29:47 +00:00
Fatima Saleem
a99f115d41
conditioned RTL with XLEN parameter ( #1579 )
2023-10-31 19:54:19 +01:00
AEzzejjari
1faaec09bc
Code_coverage: condition RTL with the debug parameter ( #1582 )
2023-10-31 17:35:59 +01:00
AEzzejjari
d92f0f76d0
Code_coverage: condition RTL with the U-MODE parameter ( #1583 )
2023-10-31 13:45:58 +01:00
AEzzejjari
4b67475fa4
Code_coverage: condition RTL with the S-MODE parameter ( #1574 )
2023-10-27 22:38:52 +02:00
André Sintzoff
7cd183b710
verible-verilog-format: apply it on core directory ( #1540 )
...
using verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format
with default configuration
Note: two files are not correctly handled by verible
- core/include/std_cache_pkg.sv
- core/cache_subsystem/cva6_hpdcache_if_adapter.sv
2023-10-18 16:36:00 +02:00
Florian Zaruba
93782ddfb5
Merge CVA6Cfg and ArianeCfg ( #1321 )
2023-09-28 11:41:38 +02:00
AEzzejjari
4641acf9d2
Code_ coverage: Remove VCS coverage pragma for BitManip ( #1469 )
2023-09-23 00:22:29 +02:00
Fatima Saleem
2ac676d931
Add Zicond Extension support in CVA6 ( #1405 )
2023-09-15 08:19:50 +02:00
JeanRochCoulon
c8202ae1ad
Decode AMOXOR_D (and similar instructions) only when XLEN=64bits ( #1355 )
2023-09-01 11:57:08 +02:00
JeanRochCoulon
434e55c457
Generate illegal opcode when execute LWU with XLEN=32 ( #1344 )
...
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-08-28 21:55:37 +02:00
JeanRochCoulon
1db42ee8da
Add variant into CVA6 parameter ( #1320 )
...
* Variane as CVA6 parameter
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* fix FPGA build
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Fix tipo in cva6.sv
* fix lint warnings
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Fix is_*_fpr functions
* remove blank lines
* set IsRVFI out of CVA6Cfg
* define config_pkg
* Fix ariane_pkg comments
* Fix Lint from André's feedbacks
* Fix parameter transmission
* Fix replace CVA6Cfg by CVA6ExtendCfg in cva6.sv
* fix add CVA6Cfg in instr_queue, instr_scan and pmp parameters
---------
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: ALLART Come <come.allart@thalesgroup.com>
2023-08-22 14:04:06 +02:00
JeanRochCoulon
279ce9fb9b
Define RVFI as cva6 parameter ( #1293 )
2023-07-19 08:21:39 +02:00
Fatima Saleem
4d2a9fe032
Resolved Lint WIDTHEXPAND warnings(1/2) ( #1303 )
2023-07-18 11:06:09 +02:00
Nils Wistoff
513bb91f82
Add Ara support ( #1024 )
...
Support Ara via a custom, parametrised accelerator interface.
cv64a6_imafdcv_sv39_config_pkg.sv enables V extension
Pre-processor constant ARIANE_ACCELERATOR_PORT enables the interface between CVA6 and Ara.
FPU is bumped to a SIMD-compatible version
Backwards compatibility should be preserved. Once this is merged, we will change the reference of Ara upstream CVA6.
-----
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Co-authored-by: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
Co-authored-by: Matteo Perotti <mperotti@iis.ee.ethz.ch>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2023-07-10 17:12:59 +02:00
Fatima Saleem
018dbc4210
Resolved Lint WIDTHTRUNC warnings(1/2) ( #1297 )
2023-07-06 11:41:25 +02:00
JeanRochCoulon
5284f828e4
declare cva6_cfg_t to pass the configuration through the hierarchy ( #1287 )
...
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-07-01 17:24:21 +02:00
JeanRochCoulon
9be687ffe4
Add coverage pragmas to exclude BITMANIP code ( #1288 )
...
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-06-30 11:45:18 -04:00
André Sintzoff
99acdc271b
decoder.sv: ZEXT.H is valid only with Zbb bitmanip extension ( fix #1234 ) ( #1236 )
...
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2023-05-22 13:27:53 +02:00
Guillaume Chauvon
80050aa21e
decoder: add missing default case for BITMANIP ( #938 )
2022-08-16 09:25:11 +02:00
Guillaume Chauvon
b6c1d04b6f
decoder.sv: fix sfence.vma when rs1 != 0 ( #933 )
...
unlike other instructions with minor opcode == PRIV,
SFENCE.VMA do not check for rs1 != 0.
Only check for rd !=0 to raise illegal instruction
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
2022-07-20 17:03:06 +02:00
