Zbigniew Chamski
|
2240bd079b
|
Add initial riscv-config input specs, validation harness and YAML outputs for CV32A65X. (#2133)
|
2024-05-21 07:21:57 +02:00 |
|
Jalali
|
95ad5fb83e
|
[HOT FIX] : Fix csr tests timeout (#2132)
|
2024-05-20 20:11:10 +02:00 |
|
Jalali
|
d4f984dbce
|
Functional coverage report in CI (#2127)
|
2024-05-17 22:58:52 +02:00 |
|
AEzzejjari
|
f8e7a7d05e
|
AXI: DvPlan modification (#1962)
|
2024-05-17 22:44:16 +02:00 |
|
AEzzejjari
|
3cd458d03c
|
Modify AXI assertion and coverage model for easy utilization of WT and HPDcache (#2125)
|
2024-05-17 22:34:36 +02:00 |
|
AngelaGonzalezMarino
|
ca0cfbcb4e
|
keep march in bootrom generation without extensions (#2121)
|
2024-05-16 16:27:22 +02:00 |
|
AngelaGonzalezMarino
|
9142fdd03a
|
integrate unified mmu with H extension (#1958)
|
2024-05-16 00:24:50 +02:00 |
|
JeanRochCoulon
|
821e2ebc3f
|
Remove localparam related to hpdcache in 65x config (#2115)
|
2024-05-16 00:20:04 +02:00 |
|
Cesar Fuguet
|
cd241cb387
|
hpdcache: update HPDcache to support parametrization (#2059)
|
2024-05-15 12:28:36 +02:00 |
|
JeanRochCoulon
|
4c58b50045
|
CV32A65X: Switch from WT to HPDCache (#2097)
* switch from WT to HPDCache for CV32A65X configuration
* Comment AXI agent asserts which are not compatible with HPDCache
|
2024-05-15 07:37:40 +00:00 |
|
JeanRochCoulon
|
dd763b4f4c
|
Rename FpuEn into RVF (#2109)
|
2024-05-15 09:16:44 +02:00 |
|
xiaoweish
|
5484a0881d
|
Running spike first to expedite error detection, especially on ISG (#2104)
|
2024-05-14 22:42:21 +02:00 |
|
xiaoweish
|
96e2d28e06
|
Fixing --iss_timeout Passing and Setting Default Timeout Values for EDA Simulators (#2105)
|
2024-05-14 22:39:47 +02:00 |
|
dependabot[bot]
|
b5def44ae3
|
Bump verif/core-v-verif from 9a34897 to 3728f31 (#2108)
|
2024-05-14 15:47:36 +02:00 |
|
dependabot[bot]
|
7215e576e9
|
Bump verif/core-v-verif from 2c55632 to 9a34897 (#2107)
|
2024-05-13 22:27:00 +02:00 |
|
Asmaa Kassimi
|
807ed7825c
|
Add Supervisor condition under Interrupt control and remove else condition. (#2098)
|
2024-05-12 21:02:57 +02:00 |
|
Florian Zaruba
|
9f40ad57cb
|
Make D independent on xlen (#2005)
A 64-bit core might very well support just single-precision.
|
2024-05-12 20:15:50 +02:00 |
|
Zbigniew Chamski
|
73590010e6
|
Set up infrastructure for Spike YAML parameter tests (#2089)
|
2024-05-03 18:23:39 +02:00 |
|
dependabot[bot]
|
85c042f58f
|
Bump verif/core-v-verif from 34d39b9 to 2c55632 (#2095)
|
2024-05-02 17:44:39 +02:00 |
|
André Sintzoff
|
c52fd2b2c9
|
Provide RISC-V ISA priv in ReadTheDocs (#2093)
* Provide RISC-V ISA for CV32A65X
* Reorder specifications in ReadTheDocs
|
2024-05-02 15:20:09 +02:00 |
|
JeanRochCoulon
|
f57efabd6b
|
doc priv: tailor machine.adoc for CV32A65X (#2092)
|
2024-05-02 10:28:23 +00:00 |
|
Jalali
|
130a526f3b
|
ISA : Cover zext with instr[24:20] != 0 (#2085)
|
2024-04-30 17:02:37 +02:00 |
|
Jalali
|
de29cfaaad
|
CSR coverage model : Remove covering S-mode fileds (#2086)
|
2024-04-30 17:02:22 +02:00 |
|
André Sintzoff
|
ecee022457
|
doc priv: tailor RISC-V privilege spec for CV32A65X (#2078)
|
2024-04-30 10:30:41 +02:00 |
|
Bruno Sá
|
96874d1ccb
|
fix hypervisor configs (#2083)
|
2024-04-29 14:58:18 +02:00 |
|
Cesar Fuguet
|
0c2108845a
|
Allow to pass custom location for the Boost library for Spike (#2082)
|
2024-04-29 12:04:20 +02:00 |
|
xiaoweish
|
3919e79f8f
|
Implement YAML anchor/alias for streamlined testlist structure (#2073)
|
2024-04-28 23:00:22 +02:00 |
|
Côme
|
261e5d3192
|
superscalar: add issue port to scoreboard (#2081)
|
2024-04-26 16:04:04 +02:00 |
|
Guillaume Chauvon
|
5e4bb5f2de
|
Fix DV_OPTS by adding UVM_VERBOSITY flag (#2080)
|
2024-04-26 14:33:33 +02:00 |
|
Guillaume Chauvon
|
1c3370950f
|
Add support for waveform in vcs-testharness (#2079)
|
2024-04-26 14:33:16 +02:00 |
|
Côme
|
779927485d
|
superscalar: duplicate decode stage (#2077)
|
2024-04-26 12:09:42 +02:00 |
|
dependabot[bot]
|
99ea7c8610
|
Bump verif/core-v-verif from d4e32fc to 34d39b9 (#2072)
|
2024-04-23 19:26:20 +02:00 |
|
JeanRochCoulon
|
3ecabdb95a
|
Cvfpu from vendor to submodule (#2070)
|
2024-04-23 14:54:42 +02:00 |
|
dependabot[bot]
|
3515908315
|
Bump verif/core-v-verif from f7bda8e to d4e32fc (#2069)
|
2024-04-23 06:31:59 +02:00 |
|
Jalali
|
5971fc755a
|
ISA coverage status (#2066)
|
2024-04-22 17:51:28 +02:00 |
|
JeanRochCoulon
|
184ccc0e58
|
Add Verible command to the CONTRIBUTING.md file (#2067)
|
2024-04-22 17:21:44 +02:00 |
|
JeanRochCoulon
|
e1d61182b7
|
Generate the cv32a65x riscv specification out of the box (#2054)
|
2024-04-22 15:34:21 +02:00 |
|
MarioOpenHWGroup
|
8a9d7a832b
|
Fix RVFI always_ff blocks (#2053)
|
2024-04-18 10:06:34 +02:00 |
|
Florian Zaruba
|
377b0de154
|
Fix SuperScalar config and add CVA6Cfg to first pass decoder (#2047)
* Add `CVA6Cfg` to first pass decoder
* Fix `verilator` `SELRANGE` warnings
* Update core/decoder.sv
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
* Update core/cva6_accel_first_pass_decoder_stub.sv
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
* Update core/decoder.sv
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
* Update core/frontend/instr_queue.sv
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
---------
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
|
2024-04-17 16:34:08 +02:00 |
|
CoralieAllioux
|
82b2d15127
|
Add ifdef for VCS fix (UNSUPPORTED_WITH) (#2041)
|
2024-04-17 15:56:52 +02:00 |
|
JeanRochCoulon
|
9a36bf2c3d
|
define riscv-isa-manual as submodule (#2052)
* remove riscv-isa-manual vendor
* Define riscv-isa-manual as submodule
|
2024-04-17 12:45:43 +00:00 |
|
Nils Wistoff
|
e84b271cff
|
ci/hyp: Fix reference to riscv-hyp-tests (#2051)
|
2024-04-17 14:01:35 +02:00 |
|
Juan Granja
|
2182aee119
|
Update ariane_xilinx.sv (#1954)
|
2024-04-17 11:18:20 +02:00 |
|
Zbigniew Chamski
|
c51fad1d0e
|
Vendorize 'riscv-config' tool in order to test/support local extensions. (#2045)
|
2024-04-16 13:56:06 +02:00 |
|
dependabot[bot]
|
75f695f665
|
Bump verif/core-v-verif from 4f9dd2a to f7bda8e (#2043)
|
2024-04-15 22:23:15 +02:00 |
|
CoralieAllioux
|
fb43d778b3
|
[UVM] Few LRM compliance fixes (#2042)
|
2024-04-15 16:44:34 +02:00 |
|
MarioOpenHWGroup
|
71ef48804a
|
[RVFI] Optimize CSRs (#1999)
|
2024-04-15 16:29:07 +02:00 |
|
JeanRochCoulon
|
e1ee77e02d
|
define WtDcacheWbufDepth as cva6 parameter and fix rvfi.svh (#2040)
|
2024-04-15 15:05:30 +02:00 |
|
Zbigniew Chamski
|
e2401d3e88
|
[HOTFIX] Add missing 'build' directory belonging in vendorized ISA docs. (#2039)
|
2024-04-15 13:07:30 +02:00 |
|
André Sintzoff
|
1e93175dd4
|
testlists for cv32a65x: add files (#2037)
|
2024-04-12 17:47:03 +02:00 |
|