Jalali
931152d205
FIx uvm seed for regression tests (light tests) ( #2828 )
...
bender-up-to-date / bender-up-to-date (push) Has been cancelled
ci / build-riscv-tests (push) Has been cancelled
ci / execute-riscv64-tests (push) Has been cancelled
ci / execute-riscv32-tests (push) Has been cancelled
Use only one uvm seed (=1) for light tests, to fix timeout error due to obi delays randomization
2025-03-14 22:43:12 +01:00
Zbigniew Chamski
c2794df8e6
[CV32A6*X] Disable Zifencei across the verification infrastructure. ( #2822 )
...
bender-up-to-date / bender-up-to-date (push) Has been cancelled
ci / build-riscv-tests (push) Has been cancelled
ci / execute-riscv64-tests (push) Has been cancelled
ci / execute-riscv32-tests (push) Has been cancelled
This MR implements the non-RTL part of CVA6 project changes needed for #2734 :
* changes to scripts
* changes to configuration files
* turn off Zifencei support in RTL configuration.
2025-03-13 06:12:47 +01:00
Jean-Roch Coulon
a3d3f07ad3
CI modifications:
...
- no test with vcs-testharness: testharness is not compatible with memories
- no asic synthesis: temporary disable, to be fixed later on
- no fpga boot: OBI does not yet support MMU/AMO, to be fixed later on
- mmu tests: OBI does not yet support MMU/AMO, to be fixed later on
- Run Spyglass on cv32a60x
- Run smoke-bench job in heavy test ci stage
- Run smoke-test on 65x and 60x
- Enable performance checks and update bench results
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2025-03-05 17:44:35 +01:00
Jean-Roch Coulon
4c3f74da5f
Disable random of UVM to shorten OBI bus latencies
2025-03-05 17:44:35 +01:00
Jalali
81426a4b85
CVXIF VERIF : update cvxif test, and remove unused tests for cv-x-if v1.0.0 ( #2808 )
...
* Run cvxif_verif_regression job only on cv32a60x, cv32a65x & vcs-uvm
2025-03-05 15:23:36 +01:00
Jalali
70972dad54
Update rvfi_tracer and cva6.py ( #2684 )
...
* RVFI Tracer : Update tracer to support interrupts
* Randomize sv_seed by default
* Change pc64 to pc
* Fixes
* cva6.py : add the capability to create a log for sv_seed
* Tracer : keep pc64 64 targets failed
* Fix UVM seed for performance tests
---------
Co-authored-by: André Sintzoff <61976467+ASintzoff@users.noreply.github.com>
2025-01-31 13:10:27 +01:00
Guillaume Chauvon
4b9cbf9223
Various fixes for CVXIF following verification. ( #2678 )
...
bender-up-to-date / bender-up-to-date (push) Has been cancelled
ci / build-riscv-tests (push) Has been cancelled
ci / execute-riscv64-tests (push) Has been cancelled
ci / execute-riscv32-tests (push) Has been cancelled
* [CVXIF] Various fixes for bugs report with CVXIF's UVM agent
* Update options and simulators to support CVXIF's UVM agent
---------
Co-authored-by: ajalali <ayoub.jalali@external.thalesgroup.com>
Co-authored-by: André Sintzoff <61976467+ASintzoff@users.noreply.github.com>
2024-12-20 13:28:49 +01:00
Valentin Thomazic
160c322f53
improve dashboard-provided log ( #2636 )
...
* Due to the increased count of warnings, provide tail of log instead of head on the dashboard
* Add tandem yaml report file on the jobs reports
* Reduce UVM Verbosity on smoke gen tests
2024-11-28 11:46:47 +01:00
JeanRochCoulon
a283d3eea2
Define cv32a60x configuration ( #2608 )
bender-up-to-date / bender-up-to-date (push) Waiting to run
ci / build-riscv-tests (push) Waiting to run
ci / execute-riscv64-tests (push) Blocked by required conditions
ci / execute-riscv32-tests (push) Blocked by required conditions
2024-11-18 15:51:21 +01:00
Zbigniew Chamski
4604195f52
[benchmarks] Pass DV_OPTS to dhrystone execution. ( #2582 )
...
ix the dhrystone execution script so that any ISS options accumulated in shell variable DV_OPTS are duly propagated to cva6.py.
2024-11-06 18:23:14 +01:00
Jean-Roch Coulon
61c38ea459
Install Verilator only if DV_SIMULATORS == veri-testharness
2024-10-23 18:24:38 +02:00
Jean-Roch Coulon
9ceab195fd
Clean-up: Remove unused regression suites and tools from CI job scripts
2024-10-23 18:24:38 +02:00
Jean-Roch Coulon
6fc8d60c14
Dhrystone_smoke.sh: smoke-smoke is done on dhrystone for the cv32a65x configuration
2024-10-23 18:24:38 +02:00
Jean-Roch Coulon
8a457272b7
Split smoke-tests.sh into 3 tests to speed-up CI timing execution of light stage
2024-10-23 18:24:38 +02:00
Jean-Roch Coulon
ce24338d5b
Run 4 iterations of coremark to improve results
2024-10-23 18:24:38 +02:00
Jean-Roch Coulon
9cfadbeded
Create dedicated linker scripts for cv32a65x configuration. When another configuration is targeted, the default linker script is used (config/genxxx/linker/link.ld). When hwconfig is targeted, linker scripts are recopied into hwconfig directory.
...
Keep only one unique linker script: link.ldi. Remove test.ld file.
2024-10-23 18:24:38 +02:00
Jean-Roch Coulon
1d0076eec3
smoke-hwconfig: run with vcs-uvm and use return0 test to speed-up CI light stage timing execution
2024-10-23 18:24:38 +02:00
JeanRochCoulon
45eaace82b
Revert "Multicommits to shorten smoke-tests duration, to declare VLEN as para…" ( #2564 )
...
This reverts commit 0877e8e446
2024-10-23 18:12:49 +02:00
JeanRochCoulon
0877e8e446
Multicommits to shorten smoke-tests duration, to declare VLEN as parameter, to improve coremark results, to implement spike.yaml/linker dedicated to 65x ( #2563 )
...
- FIX: Replace riscv_pkg:VLEN by CVA6Cfg.VLEN
- Declare VLEN as new CVA6 parameter
- smoke-hwconfig: run with vcs-uvm and use return0 tests to speed-up CI light stage timing execution
- Use dedicated linker scripts for 65x configuration.
- Use dedicated spike.yaml for 65x configuration.
- Set BHTEntries=128, cache=WT, scoreboard entries=8 to improve Coremark and Dhrystone results
- Run 4 iterations of coremark to improve results
2024-10-23 17:56:06 +02:00
Anouar
20b64e8939
Performance tb ( #2562 )
...
For reminder, the option --issrun_opts="+tb_performance_mode" allows to disable UVM features like assertion and log generation to reduce simulation time.
2024-10-23 13:11:25 +02:00
Anouar
9c3aea232f
Performance tb ( #2543 )
2024-10-11 16:57:45 +02:00
JeanRochCoulon
7ae870e02f
cv32a65x CI: Enlarge cache to increase bench result and switch from -O3 to -Os compiler option ( #2541 )
...
* .gitlab-ci.yml: Enlarge cv32a65x cache size
* Dhrystone_smoke.sh: switch from -O3 to -Os option
2024-10-11 09:42:37 +02:00
Jean-Roch Coulon
b744f9bb09
Create job dedicated to benchmark CVA6
2024-10-08 21:14:33 +02:00
JeanRochCoulon
08c81658ec
Display report at the end of dhrystone and coremark executions ( #2529 )
2024-10-04 17:52:06 +02:00
JeanRochCoulon
56532c6963
Simplify CI ( #2517 )
...
Modify CI to always check with Tandem and promote UVM TB use
2024-09-27 10:01:46 +02:00
Zbigniew Chamski
f974e105bf
Add a basic mechanism for interrupt acknowledge. ( #2502 )
2024-09-19 18:31:42 +02:00
MarioOpenHWGroup
6249bd1929
[TANDEM] CSR Params Refactor + CSR API ( #2407 )
2024-08-28 12:25:41 +02:00
valentinThomazic
28affa2346
[CI] use spike tandem on smoke-tests ( #2438 )
2024-08-22 17:04:48 +02:00
Zbigniew Chamski
89eb77a249
[Spike tandem] Fix Yaml config files for CV32A65X. Fix Questa tandem. Add workaround for AXI end-of-test asserts. ( #2436 )
2024-08-19 11:09:32 +02:00
MarioOpenHWGroup
4b51643826
TANDEM Configuration fixes ( #2420 )
2024-08-09 12:34:40 +02:00
xiaoweish
0c60bc6e3d
Add debug_test to cva6 ( #2339 )
2024-08-02 08:50:50 +02:00
Guillaume Chauvon
81671e39fa
Fixes and Update CVXIF non regression tests, regression and TB ( #2424 )
2024-08-01 16:06:24 +02:00
Zbigniew Chamski
846e1a1269
[CI DEBUG] Track cause of failures in Spike version check. ( #2360 )
2024-07-24 23:56:04 +02:00
Jalali
da1c7477ed
Increase simulation time on CSR tests ( #2361 )
2024-07-12 16:21:04 +02:00
Guillaume Chauvon
8fa590b5c3
CVXIF 1.0.0 ( #2340 )
2024-07-12 10:53:18 +02:00
Zbigniew Chamski
48ef515ba0
[Spike Yaml] Integrate Spike Yaml support. ( #2304 )
2024-07-11 08:37:37 +02:00
Jalali
2616d5e649
add UVM interrupt agent ( #2309 )
2024-07-05 11:54:34 +02:00
Guillaume Chauvon
9900d5fd19
Fix benchmark.sh with correct GCC options and order ( #2313 )
2024-07-05 11:52:27 +02:00
Mathieu Gouttenoire
3d00079c19
Prepare for LLVM ( #2251 )
2024-06-14 11:12:03 +02:00
JeanRochCoulon
cb6211bbb8
Remove cv32a6_embedded configuration ( #2246 )
2024-06-14 08:30:17 +02:00
JeanRochCoulon
4391fc4b14
Use cv32a6_imac_sv32 to generate FPGA bitstream ( #2229 )
2024-06-11 16:25:07 +02:00
Mathieu Gouttenoire
ade4c85e13
Remove extra -v in smoke-tests.sh ( #2207 )
2024-06-06 16:51:17 +02:00
xiaoweish
8cb7a8a4ed
fix gcc-14 compile error on: implicit-function-declaration, implicit-int ( #2159 )
2024-05-28 07:04:10 +02:00
slgth
9f4b2f7179
New target with MMU: cv64a6_mmu ( #2149 )
2024-05-24 13:39:00 +02:00
Cesar Fuguet
f32f51777f
Add in Github's CI a 64-bit configuration of the CVA6 using the HPDcache and restore WB cache test ( #2114 )
2024-05-21 09:51:10 +02:00
Jalali
95ad5fb83e
[HOT FIX] : Fix csr tests timeout ( #2132 )
2024-05-20 20:11:10 +02:00
Cesar Fuguet
0c2108845a
Allow to pass custom location for the Boost library for Spike ( #2082 )
2024-04-29 12:04:20 +02:00
Guillaume Chauvon
5e4bb5f2de
Fix DV_OPTS by adding UVM_VERBOSITY flag ( #2080 )
2024-04-26 14:33:33 +02:00
MarioOpenHWGroup
71ef48804a
[RVFI] Optimize CSRs ( #1999 )
2024-04-15 16:29:07 +02:00
Côme
f886713754
User config generator becomes a Python tool to work with configs ( #2003 )
2024-04-04 15:56:29 +02:00
