JeanRochCoulon
5df5a5c247
Define InstrTlbEntries, DataTlbEntries, cfg.NrLoadPipeRegs, NrStorePipeRegs, DcacheIdWidth as CVA6 parameters ( #2034 )
2024-04-12 09:06:35 +02:00
Bruno Sá
86e1408666
Hypervisor extension ( #1938 )
...
Support 64bit H extension
2024-03-21 10:28:01 +01:00
Côme
bd4b57cc64
Parametrization step 3 part 3 (last) ( #1940 )
2024-03-18 16:19:52 +01:00
Côme
4817575de9
Parametrization step 3 part 2 ( #1939 )
2024-03-18 12:06:55 +01:00
Côme
987c645bb7
Parametrization step 3 ( #1935 )
...
This is the third step for #1451 . Many values are moved but not all values are moved yet
* move NR_SB_ENTRIES & TRANS_ID_BITS
* remove default rvfi_instr_t from spike.sv
* fifo_v3: ariane_pkg::FPGA_EN becomes a param
* move FPGA_EN
* inline wt_cache_pkg::L15_SET_ASSOC
* move wt_cache_pkg::L15_WAY_WIDTH
* inline wt_cache_pkg::L1I_SET_ASSOC
* inline wt_cache_pkg::L1D_SET_ASSOC
* move wt_cache_pkg::DCACHE_CL_IDX_WIDTH
* move ICACHE_TAG_WIDTH
* move DCACHE_TAG_WIDTH
* move ICACHE_INDEX_WIDTH
* move ICACHE_SET_ASSOC
* use ICACHE_SET_ASSOC_WIDTH instead of $clog2(ICACHE_SET_ASSOC)
* move DCACHE_NUM_WORDS
* move DCACHE_INDEX_WIDTH
* move DCACHE_OFFSET_WIDTH
* move DCACHE_BYTE_OFFSET
* move DCACHE_DIRTY_WIDTH
* move DCACHE_SET_ASSOC_WIDTH
* move DCACHE_SET_ASSOC
* move CONFIG_L1I_SIZE
* move CONFIG_L1D_SIZE
* move DCACHE_LINE_WIDTH
* move ICACHE_LINE_WIDTH
* move ICACHE_USER_LINE_WIDTH
* move DCACHE_USER_LINE_WIDTH
* DATA_USER_WIDTH = DCACHE_USER_WIDTH
* move DCACHE_USER_WIDTH
* move FETCH_USER_WIDTH
* move FETCH_USER_EN
* move LOG2_INSTR_PER_FETCH
* move INSTR_PER_FETCH
* move FETCH_WIDTH
* transform SSTATUS_SD and SMODE_STATUS_READ_MASK into functions
* move [SM]_{SW,TIMER,EXT}_INTERRUPT into a structure
* move SV
* move vm_mode_t to config_pkg
* move MODE_SV
* move VPN2
* move PPNW
* move ASIDW
* move ModeW
* move XLEN_ALIGN_BYTES
* move DATA_USER_EN
* format: apply verible
2024-03-15 17:21:34 +00:00
Côme
aed4ed7c23
move functions into modules ( #1926 )
2024-03-13 17:46:33 +01:00
Côme
32a3cd56ee
Parametrization step 2 ( #1908 )
2024-03-08 22:53:42 +01:00
JeanRochCoulon
f332688fc0
Complete Design Document ( #1865 )
2024-02-23 23:09:11 +01:00
AEzzejjari
738d53af1c
Code coverage: condition RTL With parameters ( #1703 )
2023-12-13 07:52:47 +01:00
AEzzejjari
cbd3e9fe19
Modify coding style to improve CC ( #1672 )
2023-12-05 14:51:23 +01:00
André Sintzoff
c51819dcbd
verible-verilog-format: apply it on core directory ( #1668 )
...
using verible-v0.0-3430-g060bde0f/bin/verible-verilog-format
with default configuration
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2023-12-04 11:16:35 +00:00
AEzzejjari
42f29c66bd
Code coverage: Add NonIdemPotence parameter ( #1647 )
2023-11-23 23:00:21 +01:00
JeanRochCoulon
7872d0124c
improve case coding style to improve CC ( #1607 )
2023-11-10 12:15:42 +01:00
Fatima Saleem
49a4b5b4ff
resolving lint warnings... ( #1529 )
2023-10-20 15:01:42 +02:00
André Sintzoff
7cd183b710
verible-verilog-format: apply it on core directory ( #1540 )
...
using verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format
with default configuration
Note: two files are not correctly handled by verible
- core/include/std_cache_pkg.sv
- core/cache_subsystem/cva6_hpdcache_if_adapter.sv
2023-10-18 16:36:00 +02:00
AEzzejjari
ed5d42f1db
Code_coverage: Add conditions for the MMU ( #1507 )
2023-10-07 18:40:02 +02:00
Florian Zaruba
93782ddfb5
Merge CVA6Cfg and ArianeCfg ( #1321 )
2023-09-28 11:41:38 +02:00
AEzzejjari
b952b0d7c3
Code_coverage: Add conditions for the FPU ( #1442 )
2023-09-19 18:24:40 +02:00
Cesar Fuguet
c087d1223f
Support multiple outstanding load operations to the Dcache
...
The ID in the request from the load/store unit must be mirrored by the
Dcache in the response. This allows to match a given response to its
corresponding request. Responses can be given (by the Dcache) in a
different order that the one of requests.
This modification introduces a pending load table that tracks
outstanding load operations to the Dcache. The depth of this table is
a parameter in the target configuration package.
Signed-off-by: Cesar Fuguet <cesar.fuguettortolero@cea.fr>
2023-09-01 13:59:38 +02:00
JeanRochCoulon
1db42ee8da
Add variant into CVA6 parameter ( #1320 )
...
* Variane as CVA6 parameter
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* fix FPGA build
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Fix tipo in cva6.sv
* fix lint warnings
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Fix is_*_fpr functions
* remove blank lines
* set IsRVFI out of CVA6Cfg
* define config_pkg
* Fix ariane_pkg comments
* Fix Lint from André's feedbacks
* Fix parameter transmission
* Fix replace CVA6Cfg by CVA6ExtendCfg in cva6.sv
* fix add CVA6Cfg in instr_queue, instr_scan and pmp parameters
---------
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: ALLART Come <come.allart@thalesgroup.com>
2023-08-22 14:04:06 +02:00
JeanRochCoulon
279ce9fb9b
Define RVFI as cva6 parameter ( #1293 )
2023-07-19 08:21:39 +02:00
JeanRochCoulon
5284f828e4
declare cva6_cfg_t to pass the configuration through the hierarchy ( #1287 )
...
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-07-01 17:24:21 +02:00
Umer Imran
45259cfb6a
LINT: Initial changes for Lint warnings removal ( #1158 )
2023-04-24 08:22:56 +02:00
Zbigniew Chamski
a0893bce2b
Enable assertions in Verilator after migrating to Verilator v5. ( #1185 )
2023-04-19 09:35:40 +02:00
JeanRochCoulon
640eb9dc67
Replace "operator" by "operation" to avoid C++ keyword names in the SV Code. ( #1154 )
2023-04-02 16:13:59 +02:00
Cesar Fuguet
bc6128a0a0
Add ID signal to the request interface towards the data cache ( #1121 )
2023-03-19 22:32:20 +01:00
sébastien jacq
0b61544da8
Dev dcache 32bits ( #849 )
...
Reduce dcache data output width from 64 to 32 bits in cv32a6 configuration
Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com>
2022-04-11 14:54:09 +02:00
André Sintzoff
3ddf797e95
Re-organize CVA6 and APU ( #725 )
...
* Initial repository re-organization (#662 )
Initial attempt to split core from APU.
Signed-off-by: MikeOpenHWGroup <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@invia.fr>
Compile `corev_apu` (#667 )
* Makefile verilates corev_apu
* Cleanup README
* Fix URL to repo
* Cleaned-up Makefile verilates corev_apu
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
Add extended verification support (#685 )
* Makefile, riscv_pkg.sv: Select C64A6 or CV32A6
according to variant variable
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* add RVFI tracer and debug support
New files: rvfi_pkg.sv, rvfi_tracer.sv, ariane_rvfi.pkg.sv
- RVFI ports are added to ariane module
- rvfi_tracer.sv is a module added in ariane-testharness.sv
- RVFI_TRACE enables RVFI trace generation
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Move example_tb from cva6 to core-v-verif project
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile: remove useless rule for vsim
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add timescale definition when vsim is used
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add vcs support (fix #570 )
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* rvfi_tracer.sv: fix compilation error raised by vcs
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: use only 2 threads for verilator
when using 4 threads, tests from riscv-compliance and riscv-tests
test suite are randomly stucked with rv32ima configuration
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Flist.cva6: cleanup for synthesis workflow
Thales synthesis workflow does not manage comments at end of lines
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Support FPGA generation
- ariane_xilinx.sv: fix AXI bus expansion
- .gitignore, Makefile, run.tcl: fix paths
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* riscv-dbg: update to 989389b0 (to support 32-bit CVA6 debug)
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Create cva6_config_pkg to setup 32- or 64-bit configuration
According to selected configuration, Makefile calls
cv32a6_imac_sv0_config_pkg.sv or cv64a6_imac_sv39_config_pkg.sv
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Flist, ariane_wrapper.sv: add wrapper to expand rvfi and axi structures
needed for dc_shell
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* cv*a6_*_pkg.sv, riscv_pkg.sv: (Fix) Use the camel case for the localparams
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* riscv_pkg.sv: clean-up the cva6_config_pkg import
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile, ariane.sv: RVFI_TRACE define conditions RVFI port in ariane
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Add lfsr.sv to manifest
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* Directory re-organzation
* fpga/xilinx/xlnx_axi_dwidth_converter_dm_*: move files (#726 )
into the new file organisation
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* move mmu_sv32 and mmu_sv39, move bootrom, update path (#729 )
Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com>
Co-authored-by: Mike Thompson <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Co-authored-by: sébastien jacq <57099003+sjthales@users.noreply.github.com>
2021-09-24 17:21:19 +02:00
