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225 commits

Author SHA1 Message Date
Mike Thompson
733743da0f
Fix URLs to point to CV32A60X-specific files on RTDs. (#2938)
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This fixes the paths for the CV32A60X-specific documentation (from the cv32a60x branch). Whenever the cv32a60x branch is updated, the documentation will be regenerated by RTD.
2025-04-16 23:00:33 +02:00
André Sintzoff
30811d1e7e
docs: link to CV32A60X design documentation (#2931)
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2025-04-15 11:36:38 +02:00
Mike Thompson
8bcb14a2df
CV32A60X ISA (#2922)
* Bring in CV32A60X ISA from the cv32a60x branch
2025-04-15 09:40:35 +02:00
André Sintzoff
79c7c2c681
docs: add HTML generation for cv32a60x (followup PR2838) (#2845)
update global doc Makefile

Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2025-03-19 12:00:13 +01:00
André Sintzoff
21506e4c66
docs: add CV32A60X configuration in RISC-V ISA manual (#2838)
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* docs: spec_builder.py: add missing extensions
* docs: fix unpriv manual (opcode map, Zcmop)
* in opcode map, write not used when corresponding extension is disabled
* use correct condition for Zcmop extension
* docs: remove PMP chapter when no PMP
* docs: add tailored RISC-V ISA manual for CV32A60X configuration

Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2025-03-19 00:03:00 +01:00
Riccardo Tedeschi
028ce43fce
docs: add bht2lvl image (#2814)
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2025-03-07 22:01:28 +01:00
Riccardo Tedeschi
aae9b2eb66
bp: add BHT with private history (#2793)
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This PR adds a new two-level BHT predictor with private history. The new BPType parameters allow choosing between the original BHT and the new one.

Co-authored-by: Gianmarco Ottavi <ottavig91@gmail.com>
2025-03-06 09:45:45 +01:00
André Sintzoff
cbb08e8d19
docs: clarify WLRL CSR fields on CVA6 (fix #1053) (#2733)
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as priv-csrs.adoc was not yet tailored for CVA6, the file is copied
and tailored

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2025-01-23 16:48:13 +01:00
André Sintzoff
f80c507aea
docs/requirements.txt: add missing packages for RTD (#2726)
this should fix build of design documents

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2025-01-22 09:07:01 +01:00
Mike Thompson
b9886a27a2
Clean up table (#2725) 2025-01-22 08:29:35 +01:00
André Sintzoff
02092dbcf0
riscv-isa-manual: ignore mm-formal.adoc (#2723)
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as this appendix requires Java and as it is not relevant for CV32A65X

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2025-01-21 17:42:39 +01:00
Guillaume Chauvon
24c6a891b8
Docs: define values for CVXIF in 60x and 65x configuration (#2721)
Set values for X_NUM_RS in embedded configurations to 2.

Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2025-01-21 17:06:26 +01:00
André Sintzoff
b6b259914a
fix 8e5872c03 (add missing smctr.adoc file) (#2720)
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2025-01-21 16:25:18 +01:00
André Sintzoff
8e5872c03b
update riscv-isa-manual to riscv-isa-release-4f277ff-2025-01-17 (#2717)
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Since last riscv-isa-manual update (CVA6 commit 67a6ae966):
	- minor documentation changes
	- new unsupported Zsmctr extension
	- add missing asciidoctor-lists gem in dependencies/Gemfile

Gemfile update is needed for ReadTheDocs

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2025-01-21 09:56:51 +01:00
André Sintzoff
1c6b89df5b
doc: RVZicntr extension can be not supported (#2699)
counters.adoc: condition around Zicntr text
2025-01-09 14:38:49 +01:00
Munail Waqar
f7dd49efa5
Adding support for Scalar Crypto Extension (Bitmanip instructions for Cryptography, Zbkb) (#2653)
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Introduction
This PR adds support for Zbkb extension in the CVA6 core. It also adds the documentation for this extension. These changes have been tested with self-written single instruction tests and with the riscv-arch-tests. This PR will be followed by other PRs that will add complete support for the Zkn - NIST Algorithm Suite extension.

Implementation
Zbkb Extension:
Added support for the Zbkb instruction set. It essentially expands the Zbb extension with additional instructions useful in cryptography. These instructions are pack, packh, packw, brev8, unzip and zip.

Modifications
1. A new bit ZKN was added. The complete Zkn extension will be added under this bit for ease of use. This configuration will also require the RVB (bitmanip) bit to be set.
2. Updated the ALU and decoder to recognize and handle Zbkb instructions.

Documentation and Reference
The official RISC-V Cryptography Extensions Volume I was followed to ensure alignment with ratification. The relevant documentation for the Zbkb instruction was also added.

Verification
Assembly Tests:
The instructions were tested and verified with the K module of both 32 bit and 64 bit versions of the riscv-arch-tests to ensure proper functionality. These tests check for ISA compliance, edge cases and use assertions to ensure expected behavior. The tests include:
pack-01.S
packh-01.S
packw-01.S
brev8-01.S
unzip-01.S
zip-01.S
2024-12-18 22:35:41 +01:00
Zbigniew Chamski
ed89c717f7
[CV32A65X] Update PMPADDRn spec to make bit 0 ROCST 0. Update config files. (#2651)
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Update CV32A65X-annotated privileged ISA specification to reflect the fact that with PMP granularity 8 and only supported PMP address matching modes being OFF and TOR, bit 0 of the pmpaddr0..pmpaddr7 registers can be safely made read-only zero. Update riscv-config specifications and its generated files accordingly.
2024-12-09 13:22:38 +01:00
André Sintzoff
b5b316ad12
doc: fix build (cva6_frontend.adoc) (#2644)
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use defined adoc variable
2024-12-03 07:43:05 +01:00
Jalali
7eb33df0ac
Interrupt agent : Modify README also clean interrupt_pkg (#2571)
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2024-11-21 23:59:42 +01:00
AEzzejjari
7ee22cd93a
Improving frontend documentation (#2617)
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Improving frontend documentation
2024-11-20 18:56:26 +01:00
BRH
2f81dba77f
Fixed wrong axi signal (#2614)
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2024-11-20 10:45:21 +01:00
Côme
43edcd467e
document issue stage (#2598)
* Fill docs/design/design-manual/source/cva6_issue_stage.adoc
* Add variables to docs/design/design-manual/source/design.adoc
* Update port doc comments in core/issue_stage.sv, core/issue_read_operands.sv and core/scoreboard.sv
2024-11-12 20:28:25 +01:00
joncapltd
a48fe03f0e
New tutorial for coprocessor modification. (#2518)
This adds a tutorial on how to customise the example coprocessor with your own instructions and test them.
2024-11-07 13:45:10 +01:00
Côme
0687510f02
document superscalar cv32a65x (frontend + decode) (#2570)
Update the documentation of cv32a65x to make it superscalar.
This first PR only updates the documentation of the frontend and decode stages.
2024-11-04 09:29:48 +01:00
André Sintzoff
7aad781b74
doc: pmp granularity equals to 8-byte (#2572) 2024-11-04 09:27:23 +01:00
slgth
ab2283c075
doc: keep documentation in sync with the code (#2558)
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Both the ISA and design documentations use some parameters generated from the RTL (ports, parameters).
As of now, they are committed to the repository and can be out of sync with the code.

This PR removes them from the repository and freshly generates them from the code when building HTML files.

This PR also removes prebuilt HTML files (design & ISA docs) and generates them when building the top-level Read the Docs documentation (make -C docs).
2024-10-25 12:27:09 +02:00
André Sintzoff
67a6ae966c
update riscv-isa-manual to riscv-isa-release-2c07aa2-2024-10-18 (#2560)
Since last riscv-isa-manual update (CVA6 commit 3059b1cb2):
        - Privileged Architecture 1.13 ratified
        - minor documentation changes
        - wavedrom file renamed to .edn
2024-10-22 14:44:02 +02:00
Zbigniew Chamski
cff48e4c75
Add tandem verification documentation (#2553)
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2024-10-17 11:38:54 +02:00
André Sintzoff
48480c72d0 tristan doc: move files to sub-directory 2024-10-17 08:56:21 +02:00
André Sintzoff
a0f9deabff tristan: add 2024 work 2024-10-17 08:56:21 +02:00
André Sintzoff
be4a6ee364 tristan_verification_specifications.adoc: 2023 version 2024-10-17 08:56:21 +02:00
André Sintzoff
5131fb030c
doc PMP: rephrase PMP configuration description (#2540) 2024-10-11 09:12:22 +02:00
EasyIP2023
37b58243fa
docs: expand wy-nav-content width to edge of screen (#2452) 2024-08-22 18:10:19 +02:00
André Sintzoff
3059b1cb25
update riscv-isa-manual to riscv-isa-release-5ddbdd678-2024-08-01 (#2434)
since last riscv-isa-manual update (CVA6 commit 0bd8b8693)
2024-08-07 11:52:07 +02:00
slgth
6a649d6515
docs: more fixes (#2412) 2024-07-26 23:49:41 +02:00
slgth
2249202769
docs: multiple fixes (#2409) 2024-07-26 15:27:42 +02:00
slgth
e9648eaf8c
Design documentation: AsciiDoc conversion (#2399) 2024-07-25 17:18:27 +02:00
slgth
3deb95af21
cv64a6_mmu: add RISC-V ISA documentation to main page (#2393) 2024-07-25 08:37:27 +02:00
JeanRochCoulon
8d413b7c54
doc PMA: cv32a65x is always idempotent and without caches (#2377) 2024-07-22 11:15:06 +00:00
André Sintzoff
8c70976759
docs: use correct commit for riscv-isa-manual submodule (#2368)
fix after 8fa590b5c
2024-07-15 12:42:07 +00:00
Jérôme Quévremont
c4b4216981
Update cva6_requirements_specification.rst (#2364)
Specify CV-X-IF version supported: 1.0.0.
Mention of B extension (with includes the Zb* extensions, already in the specification).
Make FENCE.T as a "should" instead of "shall" as we do not have plans to integrate it yet.
2024-07-12 18:14:26 +02:00
Côme
0cbd894a7a
update port and config docs (#2363) 2024-07-12 17:00:36 +02:00
jzthales
71653038d7
Doc lsu (#2359) 2024-07-12 16:49:02 +02:00
Guillaume Chauvon
8fa590b5c3
CVXIF 1.0.0 (#2340) 2024-07-12 10:53:18 +02:00
JeanRochCoulon
58d490b461
Update PMP entry number from 16 to 64 (#2343) 2024-07-10 09:54:16 +00:00
LQUA
f44655809f
Add CV64A6_MMU core in user manual (#2324) 2024-07-09 16:49:31 +02:00
André Sintzoff
51114ee0a1
machine.adoc: add missing table (#2331)
For CVA6, add table:
Encoding of A field in PMP configuration registers
2024-07-05 23:49:20 +02:00
André Sintzoff
0bd8b8693a
update riscv-isa-manual to riscv-isa-release-ebf2e3a0b-2024-07-03 (#2323)
since last riscv-isa-manual update (CVA6 commit 105d3601b):
- minor documentation changes
- use of docs-resources submodule inside riscv-isa-manual
- requires asciidoctor-lists
2024-07-05 12:06:16 +02:00
LQUA
66caecdfe6
Add RISCV documentation for cv64a6_mmu (#2315) 2024-07-03 17:24:07 +02:00
André Sintzoff
89568b0c10
doc: clarify mtval register description when not enabled (#2271) 2024-06-19 13:00:33 +02:00