JeanRochCoulon
5e9cb5d64e
Designdoc ( #1713 )
...
* rename csr files
* Revisit the design specification skeleton
2023-12-15 14:51:32 +01:00
Florian Zaruba
344c1db4b8
Clarify pmpcfgX on illegal write combination ( fixes #1694 ) ( #1711 )
2023-12-14 15:48:40 +01:00
Jérôme Quévremont
6e41bc8b52
Updated user manual to address several configuration (second pass) ( #1696 )
2023-12-13 10:10:31 +01:00
Jérôme Quévremont
98c776dc2d
Updated user manual to address several configuration (first pass) ( #1685 )
2023-12-13 10:08:40 +01:00
JeanRochCoulon
9952bce6a6
Add embedded csr description and CSR table list ( #1662 )
2023-12-06 09:16:21 +01:00
Mike Thompson
73cd1c5eeb
Add the Zc* ISA to "Applicable Specifications" ( #1615 )
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* Add the Zc* ISA to "Applicable Specifications"
* Update cva6_requirements_specification.rst: embedded part number
* Change D and I cache information
---------
Co-authored-by: Jérôme Quévremont <jerome.quevremont@thalesgroup.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2023-11-23 09:41:08 +01:00
André Sintzoff
30cf669a32
CSR user manual: add precise trap description ( fix #1217 ) ( #1646 )
2023-11-21 19:05:50 +01:00
Côme
758511fd79
docs: fix example of OoO write-back to scoreboard ( #1621 )
...
Multiplication takes two cycles (1 cycle latency) and ALU takes one
cycle (no latency). They share the same writeback port so it is not
possible to issue an ALU instruction just after a MUL. So the example
is wrong, but it is okay if we replace MUL by LOAD as it uses another
write-back port.
Fix #1106
2023-11-13 10:59:26 +01:00
Abdul Wadood
9e47cc6947
removed c.zext.w from rv32 spec ( #1563 )
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Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
2023-10-23 14:55:05 +00:00
Abdul Wadood
43c12816f6
[DOCS] Add Zcb Instructions in CVA6 user guide and requirement specification ( #1536 )
2023-10-19 16:22:46 +02:00
Pascal Cotret
f0bd20b78c
fix most of sphinx warnings ( #1509 )
2023-10-08 14:42:57 +02:00
YazanHussnain-10x
6eea97f60e
Update CVA6 Architecture overview Figure ( #1488 )
2023-10-02 09:02:33 +02:00
Florian Zaruba
93782ddfb5
Merge CVA6Cfg and ArianeCfg ( #1321 )
2023-09-28 11:41:38 +02:00
YazanHussnain-10x
67ac2566da
Add design documentation of MMU SV32 ( #1412 )
2023-09-27 10:58:29 +02:00
Fatima Saleem
4fb073f91c
[Docs] Adding Zicond in user and requirement specs ( #1444 )
2023-09-18 23:39:26 +02:00
Asim Ahsan
0aec609196
Update programmers view ( #1259 )
2023-08-23 12:33:39 +02:00
Jérôme Quévremont
8813d96995
[Skip CI] CV-X-IF user guide: editorial changes. ( #1331 )
2023-08-23 12:31:08 +02:00
Guillaume Chauvon
a052d4f2d5
Add CVXIF chapter in user's guide ( #1289 )
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Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
2023-08-09 15:49:36 +02:00
Mohamed Aziz Frikha
6ce4705ade
Fix the reset value of MISA in user manual ( fix #1048 ) ( #1330 )
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Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-08-08 17:54:59 +02:00
Mohamed Aziz Frikha
853fb4bee5
[DOC] Adding legal values to MIP, MIE, SIP and SIE registers ( #1326 )
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Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-08-03 09:34:23 +02:00
Mohamed Aziz Frikha
b928fdfade
Adding Legal values to MTVEC and STVEC registers to fix #1060 and #1079 issues ( #1325 )
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* Adding Legal values to MTVEC and STVEC registers to fix #1060 and #1079 issues
* Updating MTVEC and STVEC description
---------
Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-07-31 11:45:00 +02:00
Florian Zaruba
dc103cd49f
Clean-up README.md and top-level directory ( #1318 )
...
* Clean-up README.md and top-level directory
This removes the duplicate `scripts` and `util` directories. Furthermore
the README is condensed by collapsing the citation and adding the
CITATION file to the repository.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
* Re-name icache req/rsp structs
The structs used to communicate with the icache have contained the
direction, which makes no sense for structs since they inherently don't
have any direction.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
---------
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
2023-07-28 08:32:48 +02:00
Mohamed Aziz Frikha
716bc7175a
Adding RISC-V behavior (WARL, WLRL, WPRI) to the specification of CSRs ( #1314 )
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Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-07-20 19:09:34 +02:00
André Sintzoff
9b4b6abe61
Traps_Interrupts_Exceptions.rst: update chapter ( #1291 )
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Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2023-07-20 10:56:09 +02:00
Mohamed Aziz Frikha
5fff2244e4
Adding Fields VS and UBE to MSTATUS in Specification to solve issue #1131 ( #1308 )
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Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-07-19 17:24:12 +02:00
Florian Zaruba
7068948245
Add first draft on PMA region ( #1295 )
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* Add first draft on PMA region
* Address code review comments
2023-07-04 15:28:44 +02:00
Mohamed Aziz Frikha
3cb54a1623
Changing Addresses of ICACHE and DCACHE to solve #1202 issue. ( #1290 )
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Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-07-01 17:27:57 +02:00
Mohamed Aziz Frikha
71e7019834
Adding WPRI in spec : register MSTATUS ( #1257 )
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Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
2023-06-08 22:42:04 +02:00
TulikaSi
4e74335884
Update CSR_Performance_Counters.rst ( #1249 )
2023-06-08 07:25:32 +02:00
AEzzejjari
8fec3db665
modifications of the AXI interface specification. ( #1251 )
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Signed-off-by: Alae Eddine Ez zejjari <alae-eddine.ez-zejjari@external.thalesgroup.com>
2023-06-08 07:22:47 +02:00
Jalali
61d5433c4b
ISA SPEC: Update RISCV_Instructions.rst ( #1247 )
2023-05-26 17:19:27 +02:00
Jalali
be58d57de1
ISA SPEC: Fix the c.addi4spn instruction's format ( #1245 )
2023-05-24 13:22:16 +02:00
Kevin Tan
20ca6b71a7
Fix typo in id_stage.md ( #1239 )
2023-05-22 11:01:13 +02:00
Jérôme Quévremont
24841d307b
Add bit manip in the requirement specificiation. ( #1226 )
2023-05-12 19:13:15 +02:00
Mohamed Aziz Frikha
b36703a80e
Add RST and YAML files generated from IP-XACT ( #1221 )
2023-05-03 16:46:16 +02:00
JeanRochCoulon
ca9fd0e41d
Update mscratch description in CSR specification ( #1216 )
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Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-05-02 17:39:41 +02:00
JeanRochCoulon
4f06aa620f
Add ip-xact directory to host all relative CSR files ( #1211 )
...
As CSR chapter has been moved to User Manual specification, CSR ip-xact is moved too.
Remove XML file duplication, the only referent XML is the 2014 version XML.
2023-04-27 11:54:52 +02:00
Umer Imran
45259cfb6a
LINT: Initial changes for Lint warnings removal ( #1158 )
2023-04-24 08:22:56 +02:00
Ethan Sifferman
9668e0fd78
updated glossary ( #1142 )
2023-04-19 22:45:03 +02:00
Jalali
64da01365a
ISA Spec : Update isa specification ( #1183 )
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Signed-off-by: Ayoub Jalali <ayoub.jalali@external.thalesgroup.com>
2023-04-19 22:40:20 +02:00
Jérôme Quévremont
d77623b5c6
[Skip CI] Various user's guide edits ( #1201 )
...
* Add mention to a single hart core
Mentions CVA6 has a single hart + minor edit.
* Update Custom_Instructions.rst
Minor edit.
2023-04-19 18:33:24 +02:00
Flavien Solt
0c3688ccb8
Fix satp spelling in documentation ( #1199 )
2023-04-19 14:12:25 +02:00
Jérôme Quévremont
ee1560fa38
[Skip CI] Adding the virtual memory section ( #1114 )
2023-04-11 11:00:36 +02:00
Mohamed Aziz Frikha
bd42e4e45f
Convert IPXACT database into 1685-2014 version ( #1132 )
2023-03-29 13:18:35 +02:00
Florian Zaruba
56ecad1ace
Add PMP section and fix addressing CV64A6 ( #1092 )
2023-03-10 07:11:32 +01:00
JeanRochCoulon
a29b231070
Specify CVA6 parameters and relative CV32a6_v5.0.0 configuration ( #1099 )
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Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-03-07 15:15:49 +01:00
JeanRochCoulon
adf99b5304
Remove email adress to avoid email robot spaming ( #1094 )
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Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-03-06 06:57:25 +01:00
JeanRochCoulon
4dcb150e37
Hot fix: cva6_scope.png file path
2023-03-05 23:35:04 +01:00
JeanRochCoulon
b9fa25a200
Move AXI chapter from design document to user manual ( #1089 )
2023-03-03 23:18:20 +01:00
JeanRochCoulon
0866495c02
transfer CSR specification from design document to user manual ( #1088 )
2023-03-03 23:13:24 +01:00
